Tser LSB Si | Maxim DS21Q55 instruction

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DS21Q55

TRANSMIT SIDE BOUNDARY TIMING (With Elastic Store Disabled)

Figure 35-19

TCLK

		CHANNEL 1	CHANNEL 2
TSER LSB Si 1		A Sa4 Sa5 Sa6 Sa7 Sa8 MSB	LSB MSB
TSYNC1
TSYNC2
		CHANNEL 1	CHANNEL 2
TSIG	D		A B C D
TSIG
TCHCLK
TCHBLK3
TLCLK4
TLINK4	DON'T CARE	DON'T CARE
TLINK4

NOTES:

1) TSYNC is in the output mode (IOCR1.1 = 1.) 2) TSYNC is in the input mode (IOCR1.1 = 0). 3) TCHBLK is programmed to block channel 2.

4) TLINK is programmed to source the Sa4 bit.

5) The signaling data at TSIG during channel 1 is normally overwritten in the transmit formatter with the CAS multiframe-alignment nibble (0000).

6) Shown is a TNAF frame boundary.

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Image 226

Maxim DS21Q55 specifications Tser LSB Si

Contents

Ordering Information FeaturesApplications Description Product Preview DS21Q55 Ansi Line Interface Feature HighlightsGeneral Clock Synthesizer Framer/Formatter System Interface Extended System Information Bus Test and DiagnosticsHdlc Controllers Control Port Product Preview DS21Q55 012103 Table of Contents PER-CHANNEL Idle Code Generation Error Count RegistersSignaling Operation Channel Blocking Registers 177 149170 186 Operating Parameters AC Timing Parameters and DiagramsMechanical Descriptions Document Revision History Block Diagram Block Diagram Figure Transmit Side Pins PIN Function Description Transmit Sync Transmit Signaling InputTSYNCx Input/Output Receive Side Pins RSYNCx Receive Signaling OutputReceive Signaling Freeze Receive Sync INT Parallel Control Port PinsTstrst MUX BTS Jtrst Jtag Test Access Port PinsA7/ALEAS Jtms Line Interface Pins Supply Pins PIN Symbol Type Description Pinout DS21Q55 PIN Description Table ESIBRD1 DVSS3DVSS4 ESIBRD2 RFSYNC4 RFSYNC2RFSYNC3 RLCLK1 RSYNC1 RSIGF3RSIGF4 RSYNC2 TNEGI1 TLINK3TLINK4 TNEGI2 TVSS3 TVSS2TVSS4 Package DS21Q55 Pin DIAGRAM, 27mm BGA AD1 Register Map Parallel PortAddress Register Name Abbreviation Pcpr SR9IMR9 PCDR1 RS3 RS1RS2 RS4 H1TC TCBR3TCBR4 H1FC Iboc RFDLM1RFDLM2 RAF Information Pcpr Special PER-CHANNEL Register OperationRegister Name Rsaoics Rsrcs Rfcs Brcs Thscs Peics Tfcs Btcs PCDR3 PCDR1PCDR2 PCDR4 Programming Model Programming Sequence Figure TEST1 TEST0 Effect on Output Pins Power-Up SequenceMaster Mode Register Mstrreg Interrupt Handling Status Registers IIR1 Information RegistersInterrupt Information Registers IIR2 Clock MAP Figure Clock MAPTransmit Clock Source T1RCR1 T1 FRAMER/FORMATTER Control RegistersT1 Control Registers OOF2 OOF1 OUT of Frame Criteria Bit 6/Receive Frame Mode Select RFM = D4 framing mode Bit 1/Receive Japanese CRC6 Enable RJCBit 5/Receive B8ZS Enable RB8ZS = B8ZS disabled T1RCR2 T1TCR1 06h Bit 7/Transmit B8ZS Enable TB8ZS = B8ZS disabledT1TCR2 TB8ZS TSLC96 Tzse FBCT2 FBCT1 TD4YM Tzbtsi TB7ZS T1 Common Control Register Bit 2/Transmit Frame Mode Select TFM = D4 framing modeT1CCR1 07h T1 Transmit Transparency T1 Receive-Side Digital-Milliwatt Code Generation T1RDMR2 T1RDMR1T1RDMR3 Information Register T1 Information RegisterINFO1 10h Alarm SET Criteria Clear Criteria T1 Alarm Criteria TableYellow Alarm RAI E1 Control Registers E1 FRAMER/FORMATTER Control RegistersE1RCR1 34h E1 SYNC/RESYNC Criteria TableE1RCR2 Rcla E1TCR1 Bit 2/Automatic E-Bit Enable Aebe Bit 0/Automatic Remote Alarm Generation ARA = disabledBit 1/Automatic AIS Generation Aais = disabled E1TCR2 Automatic Alarm Generation INFO3 E1 Information RegistersINFO7 E1 Alarm Criteria Table CCR1 Common Control and Status RegistersTCSS1 TCSS0 Transmit Clock Source IDR SR2 Interrupt Mask Register Bit 2/Receive Unframed All Ones Blue Alarm Condition RUA1IMR2 19h 1Ah SR3Lspare LDN LUP Lotc Lorc V52LNK Rdma RRA 1Bh Bit 0/Receive Remote Alarm Condition RRA = interrupt maskedIMR3 Bit 2/V5.2 Link Detected Condition V52LNK RSA1 RSA0 TMF TAF RMF Rcmf RAF SR41Ch Bit 2/Receive Multiframe Event RMF IMR4 11. I/O PIN Configuration Options IOCR1 IOCR2 Loopback Control Register Loopback ConfigurationLbcr 4Ah Information PCLR1 Per-Channel LoopbackPCLR2 PCLR4 PCLR34Dh 4Eh Error Count Registers Ercnt E1 Line Code Violation Counting Options Table Line Code Violation Count Register LcvcrT1 Line Code Violation Counting Options Table T1 Operation 42h LCVCR1Line Code Violation Count Register LCVCR2 Path Code Violation Count Register Pcvcr Framing ModeT1 Path Code Violation Counting Arrangements Table T1 Frames OUT of Sync Counting Arrangements Table Framing Mode Count MOS or F-BIT Errors What is CountedFrames Out Of Sync Count Register Foscr ERCNT.1 Information FOSCR2 Bit Counter Register EbcrFOSCR1 EBCR1 TDS0SEL 14. DS0 Monitoring FunctionTransmit DS0 Monitor Registers TDS0M RDS0SEL Receive DS0 Monitor RegistersRDS0M Signaling Operation Receive-Signaling Reinsertion at Rser Processor-Based Receive SignalingHardware-Based Receive Signaling Change Of State Signaling Control Register Force Receive Signaling All OnesReceive-Signaling Freeze Sigcr CH1-A CH1-B MSB LSBMSB LSB CH2-A CH2-B CH4-A CH4-B 60h to 6Fh Receive Signaling Registers E1 Mode, CAS FormatRS1 to RS16 CH9-A CH9-B CH9-C CH9-D RS6 RSCSE2 RSCSE1 , RSCSE2 , RSCSE3 , RSCSE4RSCSE1 RSCSE3 Processor-Based Transmit Signaling Time Slot Numbering Schemes Table 15.2.1.1 T1 Mode15.2.1.2 E1 Mode Channel Phone 50h to 5Fh Transmit Signaling Registers E1 Mode, CAS FormatTS1 to TS16 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 Transmit Signaling Registers E1 Mode, CCS Format Transmit Signaling Registers T1 Mode, ESF Format 50h to 5Bh TS3 CH8-A CH8-B TS1 CH4-A CH4-BTS2 CH6-A CH6-B TS4 SSIE1 Software Signaling Insertion Enable Registers, E1 CAS ModeSSIE2 Lcaw SSIE30Ah SSIE4 Software Signaling Insertion Enable Registers, T1 Mode Hardware-Based Transmit Signaling Idle Code Array Address Mapping Table PER-CHANNEL Idle Code GenerationBits 0-5 of Iaar Register Maps to Channel Idle Code Programming Examples Write Iaar = 40h Write Pcicr = 7Eh TCICE1 IaarPcicr TCICE2 Information RCICE1 TCICE3TCICE4 RCICE2 RCICE4 RCICE386h 87h RCBR1 Channel Blocking RegistersRCBR2 TCBR1 RCBR3RCBR4 TCBR2 TCBR4 TCBR38Eh 8Fh Elastic Stores Operation Elastic Store Control Register Bit 0/Receive Elastic Store Enable ReseEscr 4Fh Tesf Tesem Tslip Resf Resem Rslip SR51Eh IMR5 Product Preview DS21Q55 109 012103 18.1.2 E1 Mode 18.1.1 T1 ModeReceive Side Transmit Side Elastic Store Delay After Initialization TableMinimum-Delay Mode Elastic Stores Initialization 112 012103 19. G.706 INT Ermediate CRC-4 Updating E1 Mode only CRC-4 Recalculate Method Figure Transmit BOC 20. T1 BIT Oriented Code BOC ControllerReceive BOC 37h BoccBOC Control Register Rboce RBR RBF1 RBF0 Sboc SR8 Receive FDL RegisterC0h 24h IMR8 Hardware Scheme Method Additional Sa and International Si BIT Operation E1 onlyInternal Register Scheme Based On Double-Frame Method RAF Rnaf TAF Tnaf Receive Si Bits of the Align Frame Internal Register Scheme Based On CRC4 Multiframe MethodRSiAF C8h RRA CBh RSa4Receive Sa4 Bits RSa5 CDh RSa6Receive Sa6 Bits RSa7 Receive Sa8 Bits RSa8CFh Transmit Si Bits of the Align Frame TSiAFD2h TRA D5h TSa4Transmit Sa4 Bits TSa5 D7h TSa6Transmit Sa6 Bits TSa7 Transmit Sa8 Bits TSa8D9h Tsacr Hdlc Controllers Basic Operation Details Hdlc Controller Registers Table Hdlc #1 Transmit Control, Hdlc #2 Transmit Control Hdlc ConfigurationH1TC, H2TC 90h, A0h Hdlc #1 Receive Control, Hdlc #2 Receive Control Bit 0/Receive SS7 Fill In Signal Unit Delete RsfdH1RC, H2RC 31h, 32h RFHWM2 RFHWM1 RFHWM0 Receive Fifo Watermark Bytes Fifo ControlH1FC, H2FC TFLWM2 TFLWM1 TFLWM0 Transmit Fifo Watermark Bytes Register Channels Hdlc MappingReceive H2RCS1, H2RCS2, H2RCS3, H2RCS4 96h, A6h H1RTSBS, H2RTSBSRCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE 97h, 98h, 99h, 9Ah A7h, A8h, A9h, AAh TransmitTHCS7 THCS6 THCS5 THCS4 THCS3 THCS2 THCS1 THCS0 9Bh, Abh H1TTSBS, H2TTSBSTCB8SE TCB7SE TCB6SE TCB5SE TCB4SE TCB3SE TCB2SE TCB1SE 20h, 22h SR6, SR7Hdlc #1 Status Register Hdlc #2 Status Register Tmend RPE RPS Rhwm RNE Tlwm TNF IMR6, IMR7 PS2 PS1 PS0 Packet Status INFO5, INFO6INFO4 H1TFBA, H2TFBA Fifo InformationReceive Packet Bytes Available H1RPBA, H2RPBA H1TF, H2TF 22.3.5H1RF, H2RF Receive Hdlc Code Example Legacy FDL Support T1 ModeReceive Section RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0 RfdlRFDLM1, RFDLM2 Tfdl 22.6 D4/SLC-96 OperationTransmit Section Transmit FDL Register Line Interface Unit LIU Basic Network Connections Figure LIU Operation LIU Receiver Monitor Mode Receive G.703 Synchronization Signal E1 ModeTypical Monitor Application Figure LIU Transmitter Transmit BPV Error InsertionTransmit G.703 Synchronization Signal E1 Mode Transmit Short-Circuit Detector/Limiter CMI Code Mark Inversion Option Mclk PrescalerCMI Coding Figure 23.7 LIU Control Registers LIC1 E1 Mode Application Return Loss Transmit Line Build-Out Control Network Mode GC5 GC4 GC3 GC2 GC1 GC0Tlbc 7Dh ETS Lirst Ibpv TUA1 Jamux Scld Clds LIC279h Bit 7/E1/T1 Select ETS LIC3 MM1 MM0 LIC4 RT1 RT0 Internal Receive Termination ConfigurationTT1 TT0 Internal Transmit Termination Configuration MPS1 MPS0 Jamux LIC2.3 INFO2 RL3 RL2 RL1 RL0 CCR4 16h Ilut Timer RscosSR1 Lrcl Tcle Tocd Lolitc IMR1 Timer Rscos17h Recommended Circuits Basic Interface Figure 1µF Protected Interface Using Internal Receive Termination Component Specifications Transformer Specifications Table Specification Recommended Value E1 Transmit Pulse Template Figure T1 Transmit Pulse Template Figure Jitter Tolerance T1 Mode Figure Jitter Tolerance E1 Mode Figure Jitter Attenuation T1 Mode Figure Jitter Attenuation E1 Mode Figure Programmable IN-BAND Loop Code Generation and Detection RUP2 RUP1 RUP0 IbccRDN2 RDN1 RDN0 TC1 TC0 B7h TCD1Transmit Code Definition Register TCD2 RUPCD1 RUPCD2 RDNCD1 Rscc RDNCD2RSC2 RSC1 RSC0 BEh RSCD1Receive -Spare Code Definition Register RSCD2 Bert Function BC1 Bert Register DescriptionPS2 PS1 PS0 Pattern Definition E1h EIB2 EIB1 EIB0 Error Rate InsertedBC2 Length Bits BER T Interface Control Register Bit 0/BERT Enable Berten = Bert disabledBIC EAh 26h SR9Bbed Bbco BEC0 BRA1 BRA0 Brlos Bsync IMR9 Bawc BRP2 Bert Repetitive Pattern SetBRP1 BRP3 BBC2 Bert Bit CounterBBC1 BBC3 BEC2 Bert Error CounterBEC1 BEC3 Transmit Error Insertion Setup Sequence Table Payload Error Insertion FunctionStep Action ER3 ER2 ER1 ER0 Error Rate Error Rate Control RegisterBits 0 to 3/Error Insertion Rate Select Bits ER0 to ER3 ERC Value Write Read Number Of Error RegistersError Insertion Examples Table NOE1 NOEL1 Number Of Errors Left RegisterNOEL2 Frame Interleave Mode Channel Interleave ModeInterleaved PCM BUS Operation DA0 Device Position IbocIBS1 IBS0 BUS Size IBO Example Figure DS21Q55 #1 Rser DS21Q55 #3 Rser Extended System Information BUS Esib Esib Group of Four DS21Q55s Figure B0h ESIBCR1Extended System Information Bus Control Register ESIBSEL2 ESIBSEL1 ESIBSEL0 BUS BIT Driven ESIBCR2 ESI3SEL2 ESI3SEL1 ESI3SEL0 Status Output T1 Mode E1 ModeESI4SEL2 ESI4SEL1 ESI4SEL0 Status Output T1 Mode E1 Mode B1h ESIB3 ESIB1ESIB2 ESIB4 CCR2 Programmable Backplane Clock SynthesizerBPCS1 BPCS0 72h Fractional T1/E1 SupportCCR3 Tdatfmt Tgpcken Rdatfmt Rgpcken JTAG-BOUNDARY-SCAN Architecture and TEST-ACCESS Port Jtag Functional Block Diagram Figure TAP Controller State Machine Test-Logic-ResetUpdate-DR Run-Test-Idle Capture-IR Update-IRSelect-IR-Scan Shift-IR TAP Controller State Diagram Figure Instruction Codes for Ieee 1149.1 Architecture Table Instruction RegisterInstruction Selected Register Instruction Codes MSB LSB ID Code Structure TableDevice ID Codes Table Device BIT ID Bypass Register Test RegistersBoundary Scan Register Identification Register Rchblk Jtms Bpclk Jtclk Jtrst BIT PIN Symbol Type Control BIT DescriptionBoundary Scan Control Bits Table ESIBS0 Dvss Dvdd Tsig Teso NXA Tdata NXA Tsysclk Tssync TchclkESIBS1 MUX Esibrd Rsync RLOS/LOTC Rsysclk Receive Side ESF Timing Figure Rclk Rsysclk Rsysclk Rser Transmit Side D4 Timing Figure Transmit Side ESF Timing Figure Transmit Side Boundary Timing With Elastic Store Disabled Tsysclk TSER1 32.2 E1 Mode Receive Side Timing Figure Receive Side Boundary Timing With Elastic Store Disabled RSYNC2 Rmsync RSYNC3 Rchclk Rchblk 221 012103 Receive IBO Channel Interleave Mode Timing Figure Receive IBO Frame Interleave Mode Timing Figure TIMING, E1 Mode only Figure Transmit Side Timing Figure Tser LSB Si Tssync Tchclk Tchblk 228 012103 Transmit IBO Channel Interleave Mode Timing Figure Transmit IBO Frame Interleave Mode Timing Figure Operating Parameters Absolute Maximum Ratings Thermal CharacteristicsTHETA-JA θJA vs Airflow Recommended DC Operating Conditions DC CharacteristicsParameter Symbol MIN TYP MAX Capacitance AC Timing Parameters and Diagrams Parameter Symbol MIN TYP MAX Units Intel BUS Read Timing BTS = 0 / MUX = 1 Figure Intel BUS Write Timing BTS = 0 / MUX = 1 Figure Motorola BUS Timing BTS = 1 / MUX = 1 Figure 236 012103 Intel BUS Read Timing BTS = 0 / MUX = 0 Figure Motorola BUS Read Timing BTS = 1 / MUX = 0 Figure AC CHARACTERISTICS-RECEIVE Side Receive Side AC CharacteristicsParameter Symbol MIN TYP MAX Units Receive Side Timing T1 Mode Figure Receive Side TIMING, Elastic Store Enabled T1 Mode Figure Receive Line Interface Timing Figure TYP E1 Transmit AC CharacteristicsParameter Symbol MIN MAX Units Tsysclk = 8.192MHz Tsysclk = 16.384MHz Transmit Side TIMING, Elastic Store Enabled Figure Transmit Line Interface Timing Figure Mechanical Descriptions Product Preview DS21Q55 248 012103