Tsysclk = 8.192MHz Tsysclk = 16.384MHz | Maxim DS21Q55 guide

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DS21Q55

4)TSYSCLK = 8.192MHz.

5)TSYSCLK = 16.384MHz

TRANSMIT SIDE TIMING Figure 37-11

tCP

tR	tCL	tCH
tR	tF
TCLK
t D1
TESO
TSER / TSIG /	t SU
TDATA	tHD
t D2	tHD
TCHCLK
TCHBLK	t D2
	tD2
TSYNC1	tHD
TSYNC2	t SU
TSYNC2	t D2
TLCLK5	t D2
TLCLK5
	tHD
TLINK	tSU
	tSU

NOTES:

1)TSYNC is in the output mode (TCR2.2 = 1).

2)TSYNC is in the input mode (TCR2.2 = 0).

3)TSER is sampled on the falling edge of TCLK when the transmit-side elastic store is disabled.

4)TCHCLK and TCHBLK are synchronous with TCLK when the transmit-side elastic store is disabled.

5)TLINK is only sampled during F-bit locations.

6)No relationship between TCHCLK and TCHBLK and the other signals is implied.

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Image 244

Maxim DS21Q55 specifications Tsysclk = 8.192MHz Tsysclk = 16.384MHz

Contents

Features ApplicationsOrdering Information Description Product Preview DS21Q55 Ansi Feature Highlights GeneralLine Interface Clock Synthesizer Framer/Formatter System Interface Test and Diagnostics Hdlc ControllersExtended System Information Bus Control Port Product Preview DS21Q55 012103 Table of Contents Error Count Registers Signaling OperationPER-CHANNEL Idle Code Generation Channel Blocking Registers 149 170177 186 Operating Parameters AC Timing Parameters and DiagramsMechanical Descriptions Document Revision History Block Diagram Block Diagram Figure Transmit Side Pins PIN Function Description Transmit Signaling Input TSYNCxTransmit Sync Input/Output Receive Side Pins Receive Signaling Output Receive Signaling FreezeRSYNCx Receive Sync INT Parallel Control Port PinsTstrst MUX BTS Jtag Test Access Port Pins A7/ALEASJtrst Jtms Line Interface Pins Supply Pins PIN Symbol Type Description Pinout DS21Q55 PIN Description Table DVSS3 DVSS4ESIBRD1 ESIBRD2 RFSYNC2 RFSYNC3RFSYNC4 RLCLK1 RSIGF3 RSIGF4RSYNC1 RSYNC2 TLINK3 TLINK4TNEGI1 TNEGI2 TVSS3 TVSS2TVSS4 Package DS21Q55 Pin DIAGRAM, 27mm BGA AD1 Register Map Parallel PortAddress Register Name Abbreviation SR9 IMR9Pcpr PCDR1 RS1 RS2RS3 RS4 TCBR3 TCBR4H1TC H1FC RFDLM1 RFDLM2Iboc RAF Information Special PER-CHANNEL Register Operation Register NamePcpr Rsaoics Rsrcs Rfcs Brcs Thscs Peics Tfcs Btcs PCDR1 PCDR2PCDR3 PCDR4 Programming Model Programming Sequence Figure Power-Up Sequence Master Mode RegisterTEST1 TEST0 Effect on Output Pins Mstrreg Interrupt Handling Status Registers Information Registers Interrupt Information RegistersIIR1 IIR2 Clock MAP Figure Clock MAPTransmit Clock Source T1 FRAMER/FORMATTER Control Registers T1 Control RegistersT1RCR1 OOF2 OOF1 OUT of Frame Criteria Bit 1/Receive Japanese CRC6 Enable RJC Bit 5/Receive B8ZS Enable RB8ZS = B8ZS disabledBit 6/Receive Frame Mode Select RFM = D4 framing mode T1RCR2 T1TCR1 Bit 7/Transmit B8ZS Enable TB8ZS = B8ZS disabled T1TCR206h TB8ZS TSLC96 Tzse FBCT2 FBCT1 TD4YM Tzbtsi TB7ZS Bit 2/Transmit Frame Mode Select TFM = D4 framing mode T1CCR1T1 Common Control Register 07h T1 Transmit Transparency T1 Receive-Side Digital-Milliwatt Code Generation T1RDMR2 T1RDMR1T1RDMR3 T1 Information Register INFO1Information Register 10h Alarm SET Criteria Clear Criteria T1 Alarm Criteria TableYellow Alarm RAI E1 Control Registers E1 FRAMER/FORMATTER Control RegistersE1RCR1 E1 SYNC/RESYNC Criteria Table E1RCR234h Rcla E1TCR1 Bit 0/Automatic Remote Alarm Generation ARA = disabled Bit 1/Automatic AIS Generation Aais = disabledBit 2/Automatic E-Bit Enable Aebe E1TCR2 Automatic Alarm Generation INFO3 E1 Information RegistersINFO7 E1 Alarm Criteria Table CCR1 Common Control and Status RegistersTCSS1 TCSS0 Transmit Clock Source IDR SR2 Bit 2/Receive Unframed All Ones Blue Alarm Condition RUA1 IMR2Interrupt Mask Register 19h 1Ah SR3Lspare LDN LUP Lotc Lorc V52LNK Rdma RRA Bit 0/Receive Remote Alarm Condition RRA = interrupt masked IMR31Bh Bit 2/V5.2 Link Detected Condition V52LNK SR4 1ChRSA1 RSA0 TMF TAF RMF Rcmf RAF Bit 2/Receive Multiframe Event RMF IMR4 11. I/O PIN Configuration Options IOCR1 IOCR2 Loopback Configuration LbcrLoopback Control Register 4Ah Information PCLR1 Per-Channel LoopbackPCLR2 PCLR3 4DhPCLR4 4Eh Error Count Registers Ercnt Line Code Violation Count Register Lcvcr T1 Line Code Violation Counting Options TableE1 Line Code Violation Counting Options Table T1 Operation LCVCR1 Line Code Violation Count Register42h LCVCR2 Path Code Violation Count Register Pcvcr Framing ModeT1 Path Code Violation Counting Arrangements Table Framing Mode Count MOS or F-BIT Errors What is Counted Frames Out Of Sync Count Register FoscrT1 Frames OUT of Sync Counting Arrangements Table ERCNT.1 Information Bit Counter Register Ebcr FOSCR1FOSCR2 EBCR1 14. DS0 Monitoring Function Transmit DS0 Monitor RegistersTDS0SEL TDS0M RDS0SEL Receive DS0 Monitor RegistersRDS0M Signaling Operation Processor-Based Receive Signaling Hardware-Based Receive SignalingReceive-Signaling Reinsertion at Rser Change Of State Force Receive Signaling All Ones Receive-Signaling FreezeSignaling Control Register Sigcr MSB LSB MSB LSB CH2-A CH2-BCH1-A CH1-B CH4-A CH4-B Receive Signaling Registers E1 Mode, CAS Format RS1 to RS1660h to 6Fh CH9-A CH9-B CH9-C CH9-D RS6 RSCSE1 , RSCSE2 , RSCSE3 , RSCSE4 RSCSE1RSCSE2 RSCSE3 Processor-Based Transmit Signaling 15.2.1.1 T1 Mode 15.2.1.2 E1 ModeTime Slot Numbering Schemes Table Channel Phone Transmit Signaling Registers E1 Mode, CAS Format TS1 to TS1650h to 5Fh TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 Transmit Signaling Registers E1 Mode, CCS Format Transmit Signaling Registers T1 Mode, ESF Format 50h to 5Bh TS1 CH4-A CH4-B TS2 CH6-A CH6-BTS3 CH8-A CH8-B TS4 SSIE1 Software Signaling Insertion Enable Registers, E1 CAS ModeSSIE2 SSIE3 0AhLcaw SSIE4 Software Signaling Insertion Enable Registers, T1 Mode Hardware-Based Transmit Signaling Idle Code Array Address Mapping Table PER-CHANNEL Idle Code GenerationBits 0-5 of Iaar Register Maps to Channel Idle Code Programming Examples Write Iaar = 40h Write Pcicr = 7Eh Iaar PcicrTCICE1 TCICE2 Information TCICE3 TCICE4RCICE1 RCICE2 RCICE3 86hRCICE4 87h RCBR1 Channel Blocking RegistersRCBR2 RCBR3 RCBR4TCBR1 TCBR2 TCBR3 8EhTCBR4 8Fh Elastic Stores Operation Bit 0/Receive Elastic Store Enable Rese EscrElastic Store Control Register 4Fh SR5 1EhTesf Tesem Tslip Resf Resem Rslip IMR5 Product Preview DS21Q55 109 012103 18.1.2 E1 Mode 18.1.1 T1 ModeReceive Side Elastic Store Delay After Initialization Table Minimum-Delay ModeTransmit Side Elastic Stores Initialization 112 012103 19. G.706 INT Ermediate CRC-4 Updating E1 Mode only CRC-4 Recalculate Method Figure Transmit BOC 20. T1 BIT Oriented Code BOC ControllerReceive BOC Bocc BOC Control Register37h Rboce RBR RBF1 RBF0 Sboc Receive FDL Register C0hSR8 24h IMR8 Hardware Scheme Method Additional Sa and International Si BIT Operation E1 onlyInternal Register Scheme Based On Double-Frame Method RAF Rnaf TAF Tnaf Internal Register Scheme Based On CRC4 Multiframe Method RSiAFReceive Si Bits of the Align Frame C8h RRA RSa4 Receive Sa4 BitsCBh RSa5 RSa6 Receive Sa6 BitsCDh RSa7 Receive Sa8 Bits RSa8CFh Transmit Si Bits of the Align Frame TSiAFD2h TRA TSa4 Transmit Sa4 BitsD5h TSa5 TSa6 Transmit Sa6 BitsD7h TSa7 Transmit Sa8 Bits TSa8D9h Tsacr Hdlc Controllers Basic Operation Details Hdlc Controller Registers Table Hdlc Configuration H1TC, H2TCHdlc #1 Transmit Control, Hdlc #2 Transmit Control 90h, A0h Bit 0/Receive SS7 Fill In Signal Unit Delete Rsfd H1RC, H2RCHdlc #1 Receive Control, Hdlc #2 Receive Control 31h, 32h Fifo Control H1FC, H2FCRFHWM2 RFHWM1 RFHWM0 Receive Fifo Watermark Bytes TFLWM2 TFLWM1 TFLWM0 Transmit Fifo Watermark Bytes Hdlc Mapping ReceiveRegister Channels H2RCS1, H2RCS2, H2RCS3, H2RCS4 96h, A6h H1RTSBS, H2RTSBSRCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE 97h, 98h, 99h, 9Ah A7h, A8h, A9h, AAh TransmitTHCS7 THCS6 THCS5 THCS4 THCS3 THCS2 THCS1 THCS0 9Bh, Abh H1TTSBS, H2TTSBSTCB8SE TCB7SE TCB6SE TCB5SE TCB4SE TCB3SE TCB2SE TCB1SE SR6, SR7 Hdlc #1 Status Register Hdlc #2 Status Register20h, 22h Tmend RPE RPS Rhwm RNE Tlwm TNF IMR6, IMR7 PS2 PS1 PS0 Packet Status INFO5, INFO6INFO4 Fifo Information Receive Packet Bytes AvailableH1TFBA, H2TFBA H1RPBA, H2RPBA H1TF, H2TF 22.3.5H1RF, H2RF Receive Hdlc Code Example Legacy FDL Support T1 ModeReceive Section RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0 RfdlRFDLM1, RFDLM2 22.6 D4/SLC-96 Operation Transmit SectionTfdl Transmit FDL Register Line Interface Unit LIU Basic Network Connections Figure LIU Operation LIU Receiver Monitor Mode Receive G.703 Synchronization Signal E1 ModeTypical Monitor Application Figure Transmit BPV Error Insertion Transmit G.703 Synchronization Signal E1 ModeLIU Transmitter Transmit Short-Circuit Detector/Limiter CMI Code Mark Inversion Option Mclk PrescalerCMI Coding Figure 23.7 LIU Control Registers LIC1 E1 Mode Application Return Loss Network Mode GC5 GC4 GC3 GC2 GC1 GC0 TlbcTransmit Line Build-Out Control 7Dh LIC2 79hETS Lirst Ibpv TUA1 Jamux Scld Clds Bit 7/E1/T1 Select ETS LIC3 MM1 MM0 RT1 RT0 Internal Receive Termination Configuration TT1 TT0 Internal Transmit Termination ConfigurationLIC4 MPS1 MPS0 Jamux LIC2.3 INFO2 RL3 RL2 RL1 RL0 CCR4 Ilut Timer Rscos SR116h Lrcl Tcle Tocd Lolitc IMR1 Timer Rscos17h Recommended Circuits Basic Interface Figure 1µF Protected Interface Using Internal Receive Termination Component Specifications Transformer Specifications Table Specification Recommended Value E1 Transmit Pulse Template Figure T1 Transmit Pulse Template Figure Jitter Tolerance T1 Mode Figure Jitter Tolerance E1 Mode Figure Jitter Attenuation T1 Mode Figure Jitter Attenuation E1 Mode Figure Programmable IN-BAND Loop Code Generation and Detection Ibcc RDN2 RDN1 RDN0RUP2 RUP1 RUP0 TC1 TC0 TCD1 Transmit Code Definition RegisterB7h TCD2 RUPCD1 RUPCD2 RDNCD1 Rscc RDNCD2RSC2 RSC1 RSC0 RSCD1 Receive -Spare Code Definition RegisterBEh RSCD2 Bert Function BC1 Bert Register DescriptionPS2 PS1 PS0 Pattern Definition EIB2 EIB1 EIB0 Error Rate Inserted BC2E1h Length Bits Bit 0/BERT Enable Berten = Bert disabled BICBER T Interface Control Register EAh 26h SR9Bbed Bbco BEC0 BRA1 BRA0 Brlos Bsync IMR9 Bawc Bert Repetitive Pattern Set BRP1BRP2 BRP3 Bert Bit Counter BBC1BBC2 BBC3 Bert Error Counter BEC1BEC2 BEC3 Transmit Error Insertion Setup Sequence Table Payload Error Insertion FunctionStep Action Error Rate Control Register Bits 0 to 3/Error Insertion Rate Select Bits ER0 to ER3ER3 ER2 ER1 ER0 Error Rate ERC Number Of Error Registers Error Insertion Examples TableValue Write Read NOE1 NOEL1 Number Of Errors Left RegisterNOEL2 Frame Interleave Mode Channel Interleave ModeInterleaved PCM BUS Operation DA0 Device Position IbocIBS1 IBS0 BUS Size IBO Example Figure DS21Q55 #1 Rser DS21Q55 #3 Rser Extended System Information BUS Esib Esib Group of Four DS21Q55s Figure ESIBCR1 Extended System Information Bus Control RegisterB0h ESIBSEL2 ESIBSEL1 ESIBSEL0 BUS BIT Driven ESI3SEL2 ESI3SEL1 ESI3SEL0 Status Output T1 Mode E1 Mode ESI4SEL2 ESI4SEL1 ESI4SEL0 Status Output T1 Mode E1 ModeESIBCR2 B1h ESIB1 ESIB2ESIB3 ESIB4 CCR2 Programmable Backplane Clock SynthesizerBPCS1 BPCS0 Fractional T1/E1 Support CCR372h Tdatfmt Tgpcken Rdatfmt Rgpcken JTAG-BOUNDARY-SCAN Architecture and TEST-ACCESS Port Jtag Functional Block Diagram Figure Test-Logic-Reset Update-DRTAP Controller State Machine Run-Test-Idle Update-IR Select-IR-ScanCapture-IR Shift-IR TAP Controller State Diagram Figure Instruction Codes for Ieee 1149.1 Architecture Table Instruction RegisterInstruction Selected Register Instruction Codes ID Code Structure Table Device ID Codes TableMSB LSB Device BIT ID Test Registers Boundary Scan RegisterBypass Register Identification Register BIT PIN Symbol Type Control BIT Description Boundary Scan Control Bits TableRchblk Jtms Bpclk Jtclk Jtrst ESIBS0 Tsig Teso NXA Tdata NXA Tsysclk Tssync Tchclk ESIBS1 MUXDvss Dvdd Esibrd Rsync RLOS/LOTC Rsysclk Receive Side ESF Timing Figure Rclk Rsysclk Rsysclk Rser Transmit Side D4 Timing Figure Transmit Side ESF Timing Figure Transmit Side Boundary Timing With Elastic Store Disabled Tsysclk TSER1 32.2 E1 Mode Receive Side Timing Figure Receive Side Boundary Timing With Elastic Store Disabled RSYNC2 Rmsync RSYNC3 Rchclk Rchblk 221 012103 Receive IBO Channel Interleave Mode Timing Figure Receive IBO Frame Interleave Mode Timing Figure TIMING, E1 Mode only Figure Transmit Side Timing Figure Tser LSB Si Tssync Tchclk Tchblk 228 012103 Transmit IBO Channel Interleave Mode Timing Figure Transmit IBO Frame Interleave Mode Timing Figure Operating Parameters Absolute Maximum Ratings Thermal CharacteristicsTHETA-JA θJA vs Airflow DC Characteristics Parameter Symbol MIN TYP MAXRecommended DC Operating Conditions Capacitance AC Timing Parameters and Diagrams Parameter Symbol MIN TYP MAX Units Intel BUS Read Timing BTS = 0 / MUX = 1 Figure Intel BUS Write Timing BTS = 0 / MUX = 1 Figure Motorola BUS Timing BTS = 1 / MUX = 1 Figure 236 012103 Intel BUS Read Timing BTS = 0 / MUX = 0 Figure Motorola BUS Read Timing BTS = 1 / MUX = 0 Figure AC CHARACTERISTICS-RECEIVE Side Receive Side AC CharacteristicsParameter Symbol MIN TYP MAX Units Receive Side Timing T1 Mode Figure Receive Side TIMING, Elastic Store Enabled T1 Mode Figure Receive Line Interface Timing Figure Transmit AC Characteristics Parameter Symbol MINTYP E1 MAX Units Tsysclk = 8.192MHz Tsysclk = 16.384MHz Transmit Side TIMING, Elastic Store Enabled Figure Transmit Line Interface Timing Figure Mechanical Descriptions Product Preview DS21Q55 248 012103