Maxim DS21Q55 specifications Interrupt Handling, Status Registers

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6.2 Interrupt Handling

Various alarms, conditions, and events in the DS21Q55 can cause interrupts. For simplicity, these are all referred to as events in this explanation. All STATUS registers can be programmed to produce interrupts. Each status register has an associated interrupt mask register. For example, SR1 (Status Register 1) has an interrupt control register called IMR1 (Interrupt Mask Register 1). Status registers are the only sources of interrupts. On power- up, all writeable registers are automatically cleared. Since bits in the IMRx registers have to be set = 1 to allow a particular event to cause an interrupt, no interrupts can occur until the host selects which events are to product interrupts. Since there are potentially many sources of interrupts, several features are available to help sort out and identify which event is causing an interrupt. When an interrupt occurs, the host should first read the IIR1, IIR2, and IIR3 regis ters (interrupt information registers) to identify which status register(s) is producing the interrupt. Once that is determined, the individual status register or registers can be examined to determine the exact source. In eight port configurations, two DS21Q55s can be connected together via the 3-wire ESIB feature. This allows all eight transceivers to be interrogated by a single CPU port read cycle. The host can determine the synchronization status or interrupt status of all eight devices with a single read. The ESIB feature also allows the user to select from various events to be examined via this method. For more information, see the ESIB section in this data sheet.

Once an interrupt has occurred, the interrupt handler routine should set the INTDIS bit (CCR3.6) to stop further activity on the interrupt pin. After all interrupts have been determined and processed, the interrupt hander routine should re-enable interrupts by setting the INTDIS bit = 0.

6.3 Status Registers

When a particular event or condition has occurred (or is still occurring in the case of conditions), the appropriate bit in a status register will be set to a one. All of the status registers operate in a latched fashion, which means that if an event or condition occurs a bit is set to a one. It will remain set until the user reads that bit. An event bit will be cleared when it is read and it will not be set again until the event has occurred again. Condition bits such as RBL, RLOS, etc., will remain set if the alarm is still present.

The user will always proceed a read of any of the status registers with a write. The byte written to the register will inform the DS21Q55 which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit location, the read register will be updated with the latest information. When a zero is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status registers will be immediately followed by a read of the same register. This write-read scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS21Q55 with higher order languages.

Status register bits are divided into two groups, condition bits and event bits. Condition bits are typically network conditions such as loss of sync, or all ones detect. Event bits are typically markers such as the one-second timer, elastic store slip, etc. Each status register bit is labeled as a condition or event bit. Some of the status registers have bits for both the detection of a condition and the clearance of the condition. For example, SR2 has a bit that is set when the device goes into a loss of sync state (SR2.0, a condition bit) and a bit that is set (SR2.4, an event bit ) when the loss of sync condition clears (goes in sync). Some of the status register bits (condition bits) do not have a separate bit for the “condition clear” event but rather the status bit can produce interrupts on both edges, setting, and clearing. These bits are

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