Maxim DS21Q55 TSYNCx, Transmit Sync, Input/Output, TSSYNCx, Transmit System Sync, TSIGx, TPOSOx

Product Preview	DS21Q55
Signal Name:	TSYNCx
Signal Description:	Transmit Sync
Signal Type:	Input/Output

A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Can be programmed to output either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set via IOCR1.3 to output double -wide pulses at signaling frames in T1 mode.

Signal Name:	TSSYNCx
Signal Description:	Transmit System Sync
Signal Type:	Input

Only used when the transmit -side elastic store is enabled. A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Should be tied low in applications that do not use the transmit -side elastic store.

Signal Name:	TSIGx
Signal Description:	Transmit Signaling Input
Signal Type:	Input

When enabled, this input will sample signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge of TCLK when the transmit -side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit -side elastic store is enabled.

Signal Name:	TPOSOx
Signal Description:	Transmit Positive Data Output
Signal Type:	Output

Updated on the rising edge of TCLKO with the bipolar data out of the transmit -side formatter. Can be programmed to source NRZ data via the output-data format (IOCR1.0)-control bit. This pin is normally tied to TPOSI.

Signal Name:	TNEGOx
Signal Description:	Transmit Negative Data Output
Signal Type:	Output

Updated on the rising edge of TCLKO with the bipolar data out of the transmit -side formatter. This pin is normally tied to

TNEGI.

Signal Name:	TCLKOx
Signal Description:	Transmit Clock Output
Signal Type:	Output

Buffered clock that is used to clock data through the transmit -side formatter (either TCLK or RCLKI). This pin is normally tied to TCLKI.

Signal Name:	TPOSIx
Signal Description:	Transmit Positive Data Input
Signal Type:	Input

Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications.

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