Maxim DS21Q55 specifications E1 SYNC/RESYNC Criteria Table, E1RCR2, 34h, Rcla

Product Preview			DS21Q55
E1 SYNC/RESYNC CRITERIA Table 11-1
FRAME OR	SYNC CRITERIA	RESYNC CRITERIA	ITU SPEC.
MULTIFRAME
LEVEL
FAS	FAS present in frame N	Three consecutive incorrect FAS	G.706
	and N + 2, and FAS not	received	4.1.1
	present in frame N + 1	Alternate: (E1RCR1.2 = 1) The	4.1.2
		above criteria is met or three
		consecutive incorrect bit 2 of non-
		FAS received
CRC4	Two valid MF alignment	915 or more CRC4 code words out	G.706
	words found within 8ms	of 1000 received in error	4.2 and 4.3.2
CAS	Valid MF alignment word	Two consecutive MF alignment	G.732 5.2
	found and previous	words received in error
	timeslot 16 contains code
	other than all zeros
Register Name:	E1RCR2
Register Description:	E1 Receive Control Register 2
Register Address:	34h

Bit #

Name

Default

7	6	5	4	3	2	1	0
Sa8S	Sa7S	Sa6S	Sa5S	Sa4S	-	-	RCLA
0	0	0	0	0	0	0	0

Bit 0/Receive Carrier Loss (RCL) Alternate Criteria (RCLA). Defines the criteria for a Receive Carrier Loss condition for both the framer and Line Interface (LIU)

0 = RCL declared upon 255 consecutive zeros (125µs) 1 = RCL declared upon 2048 consecutive zeros (1ms)

Bit 1/Unused, must be set to zero for proper operation.

Bit 2/Unused, must be set to zero for proper operation.

Bit 3/Sa4 -Bit Select(Sa4S). Set to one to have RLCLK pulse at the Sa4-bit position; set to zero to force RLCLK low during Sa4-bit position. See Functional Timing Diagrams for details.

Bit 4/Sa5 -Bit Select(Sa5S). Set to one to have RLCLK pulse at the Sa5-bit position; set to zero to force RLCLK low during Sa5-bit position. See Functional Timing Diagrams for details.

Bit 5/Sa6 -Bit Select(Sa6S). Set to one to have RLCLK pulse at the Sa6-bit position; set to zero to force RLCLK low during Sa6-bit position. See Functional Timing Diagrams for details.

Bit 6/Sa7 -Bit Select(Sa7S). Set to one to have RLCLK pulse at the Sa7-bit position; set to zero to force RLCLK low during Sa7-bit position. See Functional Timing Diagrams for details.

Bit 7/Sa8 -Bit Select (Sa8S). Set to one to have RLCLK pulse at the Sa8-bit position; set to zero to force RLCLK low during Sa8-bit position. See Functional Timing Diagrams for details.

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