Receive Side ESF Timing Figure | Maxim DS21Q55 guide

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DS21Q55

RECEIVE SIDE ESF TIMING Figure 35-2

FRAME#

RSYNC1

RFSYNC

RSYNC2

RSYNC3

RLCLK 4

RLINK5

TLCLK 6

TLINK 7

			1			2			3			4			5			6			7			8			9			10			11			12			13			14			15			16			17			18			19			20			21			22			23			24				1			2			3			4			5

NOTES:

1)RSYNC in frame mode (IOCR1.4 = 0) and double wide frame sync is not enabled (IOCR1.6 = 0).

2)RSYNC in frame mode (IOCR1.4 = 0) and double wide frame sync is enabled (IOCR1.6 = 1).

3) RSYNC in multiframe mode (IOCR1.4 = 1). 4) ZBTSI mode disabled (T1RCR2.2 = 0).

5) RLINK data (FDL bits) is updated one bit time before odd frames and held for two frames. 6) ZBTSI mode is enabled (T1RCR2.2 = 1).

7) RLINK data (Z bits) is updated one bit time before odd frames and held for four frames.

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Image 209

Maxim DS21Q55 specifications Receive Side ESF Timing Figure

Contents

Applications FeaturesOrdering Information Description Product Preview DS21Q55 Ansi General Feature HighlightsLine Interface Clock Synthesizer System Interface Framer/Formatter Hdlc Controllers Test and DiagnosticsExtended System Information Bus Control Port Product Preview DS21Q55 012103 Table of Contents Signaling Operation Error Count RegistersPER-CHANNEL Idle Code Generation Channel Blocking Registers 170 149177 186 Mechanical Descriptions AC Timing Parameters and DiagramsOperating Parameters Document Revision History Block Diagram Figure Block Diagram PIN Function Description Transmit Side Pins TSYNCx Transmit Signaling InputTransmit Sync Input/Output Receive Side Pins Receive Signaling Freeze Receive Signaling OutputRSYNCx Receive Sync Tstrst Parallel Control Port PinsINT BTS MUX A7/ALEAS Jtag Test Access Port PinsJtrst Jtms Line Interface Pins Supply Pins Pinout DS21Q55 PIN Description Table PIN Symbol Type Description DVSS4 DVSS3ESIBRD1 ESIBRD2 RFSYNC3 RFSYNC2RFSYNC4 RLCLK1 RSIGF4 RSIGF3RSYNC1 RSYNC2 TLINK4 TLINK3TNEGI1 TNEGI2 TVSS4 TVSS2TVSS3 AD1 Package DS21Q55 Pin DIAGRAM, 27mm BGA Address Register Name Abbreviation Parallel PortRegister Map IMR9 SR9Pcpr PCDR1 RS2 RS1RS3 RS4 TCBR4 TCBR3H1TC H1FC RFDLM2 RFDLM1Iboc RAF Information Register Name Special PER-CHANNEL Register OperationPcpr Rsaoics Rsrcs Rfcs Brcs Thscs Peics Tfcs Btcs PCDR2 PCDR1PCDR3 PCDR4 Programming Sequence Figure Programming Model Master Mode Register Power-Up SequenceTEST1 TEST0 Effect on Output Pins Mstrreg Status Registers Interrupt Handling Interrupt Information Registers Information RegistersIIR1 IIR2 Transmit Clock Source Clock MAPClock MAP Figure T1 Control Registers T1 FRAMER/FORMATTER Control RegistersT1RCR1 OOF2 OOF1 OUT of Frame Criteria Bit 5/Receive B8ZS Enable RB8ZS = B8ZS disabled Bit 1/Receive Japanese CRC6 Enable RJCBit 6/Receive Frame Mode Select RFM = D4 framing mode T1RCR2 T1TCR1 T1TCR2 Bit 7/Transmit B8ZS Enable TB8ZS = B8ZS disabled06h TB8ZS TSLC96 Tzse FBCT2 FBCT1 TD4YM Tzbtsi TB7ZS T1CCR1 Bit 2/Transmit Frame Mode Select TFM = D4 framing modeT1 Common Control Register 07h T1 Receive-Side Digital-Milliwatt Code Generation T1 Transmit Transparency T1RDMR3 T1RDMR1T1RDMR2 INFO1 T1 Information RegisterInformation Register 10h Yellow Alarm RAI T1 Alarm Criteria TableAlarm SET Criteria Clear Criteria E1RCR1 E1 FRAMER/FORMATTER Control RegistersE1 Control Registers E1RCR2 E1 SYNC/RESYNC Criteria Table34h Rcla E1TCR1 Bit 1/Automatic AIS Generation Aais = disabled Bit 0/Automatic Remote Alarm Generation ARA = disabledBit 2/Automatic E-Bit Enable Aebe E1TCR2 Automatic Alarm Generation INFO7 E1 Information RegistersINFO3 E1 Alarm Criteria Table TCSS1 TCSS0 Transmit Clock Source Common Control and Status RegistersCCR1 SR2 IDR IMR2 Bit 2/Receive Unframed All Ones Blue Alarm Condition RUA1Interrupt Mask Register 19h Lspare LDN LUP Lotc Lorc V52LNK Rdma RRA SR31Ah IMR3 Bit 0/Receive Remote Alarm Condition RRA = interrupt masked1Bh Bit 2/V5.2 Link Detected Condition V52LNK 1Ch SR4RSA1 RSA0 TMF TAF RMF Rcmf RAF Bit 2/Receive Multiframe Event RMF IMR4 IOCR1 11. I/O PIN Configuration Options IOCR2 Lbcr Loopback ConfigurationLoopback Control Register 4Ah Information PCLR2 Per-Channel LoopbackPCLR1 4Dh PCLR3PCLR4 4Eh Ercnt Error Count Registers T1 Line Code Violation Counting Options Table Line Code Violation Count Register LcvcrE1 Line Code Violation Counting Options Table T1 Operation Line Code Violation Count Register LCVCR142h LCVCR2 T1 Path Code Violation Counting Arrangements Table Framing ModePath Code Violation Count Register Pcvcr Frames Out Of Sync Count Register Foscr Framing Mode Count MOS or F-BIT Errors What is CountedT1 Frames OUT of Sync Counting Arrangements Table ERCNT.1 Information FOSCR1 Bit Counter Register EbcrFOSCR2 EBCR1 Transmit DS0 Monitor Registers 14. DS0 Monitoring FunctionTDS0SEL TDS0M RDS0M Receive DS0 Monitor RegistersRDS0SEL Signaling Operation Hardware-Based Receive Signaling Processor-Based Receive SignalingReceive-Signaling Reinsertion at Rser Change Of State Receive-Signaling Freeze Force Receive Signaling All OnesSignaling Control Register Sigcr MSB LSB CH2-A CH2-B MSB LSBCH1-A CH1-B CH4-A CH4-B RS1 to RS16 Receive Signaling Registers E1 Mode, CAS Format60h to 6Fh CH9-A CH9-B CH9-C CH9-D RS6 RSCSE1 RSCSE1 , RSCSE2 , RSCSE3 , RSCSE4RSCSE2 RSCSE3 Processor-Based Transmit Signaling 15.2.1.2 E1 Mode 15.2.1.1 T1 ModeTime Slot Numbering Schemes Table Channel Phone TS1 to TS16 Transmit Signaling Registers E1 Mode, CAS Format50h to 5Fh TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 Transmit Signaling Registers E1 Mode, CCS Format 50h to 5Bh Transmit Signaling Registers T1 Mode, ESF Format TS2 CH6-A CH6-B TS1 CH4-A CH4-BTS3 CH8-A CH8-B TS4 SSIE2 Software Signaling Insertion Enable Registers, E1 CAS ModeSSIE1 0Ah SSIE3Lcaw SSIE4 Software Signaling Insertion Enable Registers, T1 Mode Hardware-Based Transmit Signaling Bits 0-5 of Iaar Register Maps to Channel PER-CHANNEL Idle Code GenerationIdle Code Array Address Mapping Table Write Iaar = 40h Write Pcicr = 7Eh Idle Code Programming Examples Pcicr IaarTCICE1 TCICE2 Information TCICE4 TCICE3RCICE1 RCICE2 86h RCICE3RCICE4 87h RCBR2 Channel Blocking RegistersRCBR1 RCBR4 RCBR3TCBR1 TCBR2 8Eh TCBR3TCBR4 8Fh Elastic Stores Operation Escr Bit 0/Receive Elastic Store Enable ReseElastic Store Control Register 4Fh 1Eh SR5Tesf Tesem Tslip Resf Resem Rslip IMR5 Product Preview DS21Q55 109 012103 Receive Side 18.1.1 T1 Mode18.1.2 E1 Mode Minimum-Delay Mode Elastic Store Delay After Initialization TableTransmit Side Elastic Stores Initialization 112 012103 CRC-4 Recalculate Method Figure 19. G.706 INT Ermediate CRC-4 Updating E1 Mode only Receive BOC 20. T1 BIT Oriented Code BOC ControllerTransmit BOC BOC Control Register Bocc37h Rboce RBR RBF1 RBF0 Sboc C0h Receive FDL RegisterSR8 24h IMR8 Internal Register Scheme Based On Double-Frame Method Additional Sa and International Si BIT Operation E1 onlyHardware Scheme Method Rnaf RAF Tnaf TAF RSiAF Internal Register Scheme Based On CRC4 Multiframe MethodReceive Si Bits of the Align Frame C8h RRA Receive Sa4 Bits RSa4CBh RSa5 Receive Sa6 Bits RSa6CDh RSa7 CFh RSa8Receive Sa8 Bits D2h TSiAFTransmit Si Bits of the Align Frame TRA Transmit Sa4 Bits TSa4D5h TSa5 Transmit Sa6 Bits TSa6D7h TSa7 D9h TSa8Transmit Sa8 Bits Tsacr Basic Operation Details Hdlc Controllers Hdlc Controller Registers Table H1TC, H2TC Hdlc ConfigurationHdlc #1 Transmit Control, Hdlc #2 Transmit Control 90h, A0h H1RC, H2RC Bit 0/Receive SS7 Fill In Signal Unit Delete RsfdHdlc #1 Receive Control, Hdlc #2 Receive Control 31h, 32h H1FC, H2FC Fifo ControlRFHWM2 RFHWM1 RFHWM0 Receive Fifo Watermark Bytes TFLWM2 TFLWM1 TFLWM0 Transmit Fifo Watermark Bytes Receive Hdlc MappingRegister Channels H2RCS1, H2RCS2, H2RCS3, H2RCS4 RCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE H1RTSBS, H2RTSBS96h, A6h THCS7 THCS6 THCS5 THCS4 THCS3 THCS2 THCS1 THCS0 Transmit97h, 98h, 99h, 9Ah A7h, A8h, A9h, AAh TCB8SE TCB7SE TCB6SE TCB5SE TCB4SE TCB3SE TCB2SE TCB1SE H1TTSBS, H2TTSBS9Bh, Abh Hdlc #1 Status Register Hdlc #2 Status Register SR6, SR720h, 22h Tmend RPE RPS Rhwm RNE Tlwm TNF IMR6, IMR7 INFO4 INFO5, INFO6PS2 PS1 PS0 Packet Status Receive Packet Bytes Available Fifo InformationH1TFBA, H2TFBA H1RPBA, H2RPBA H1RF, H2RF 22.3.5H1TF, H2TF Receive Section Legacy FDL Support T1 ModeReceive Hdlc Code Example RFDLM1, RFDLM2 RfdlRFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0 Transmit Section 22.6 D4/SLC-96 OperationTfdl Transmit FDL Register Basic Network Connections Figure Line Interface Unit LIU LIU Receiver LIU Operation Typical Monitor Application Figure Receive G.703 Synchronization Signal E1 ModeMonitor Mode Transmit G.703 Synchronization Signal E1 Mode Transmit BPV Error InsertionLIU Transmitter Transmit Short-Circuit Detector/Limiter CMI Coding Figure Mclk PrescalerCMI Code Mark Inversion Option LIC1 23.7 LIU Control Registers Application Return Loss E1 Mode Tlbc Network Mode GC5 GC4 GC3 GC2 GC1 GC0Transmit Line Build-Out Control 7Dh 79h LIC2ETS Lirst Ibpv TUA1 Jamux Scld Clds Bit 7/E1/T1 Select ETS MM1 MM0 LIC3 TT1 TT0 Internal Transmit Termination Configuration RT1 RT0 Internal Receive Termination ConfigurationLIC4 MPS1 MPS0 Jamux LIC2.3 RL3 RL2 RL1 RL0 INFO2 CCR4 SR1 Ilut Timer Rscos16h Lrcl Tcle Tocd Lolitc 17h Timer RscosIMR1 1µF Recommended Circuits Basic Interface Figure Protected Interface Using Internal Receive Termination Specification Recommended Value Component Specifications Transformer Specifications Table T1 Transmit Pulse Template Figure E1 Transmit Pulse Template Figure Jitter Tolerance E1 Mode Figure Jitter Tolerance T1 Mode Figure Jitter Attenuation E1 Mode Figure Jitter Attenuation T1 Mode Figure Programmable IN-BAND Loop Code Generation and Detection RDN2 RDN1 RDN0 IbccRUP2 RUP1 RUP0 TC1 TC0 Transmit Code Definition Register TCD1B7h TCD2 RUPCD2 RUPCD1 RDNCD1 RSC2 RSC1 RSC0 RDNCD2Rscc Receive -Spare Code Definition Register RSCD1BEh RSCD2 Bert Function PS2 PS1 PS0 Pattern Definition Bert Register DescriptionBC1 BC2 EIB2 EIB1 EIB0 Error Rate InsertedE1h Length Bits BIC Bit 0/BERT Enable Berten = Bert disabledBER T Interface Control Register EAh Bbed Bbco BEC0 BRA1 BRA0 Brlos Bsync SR926h Bawc IMR9 BRP1 Bert Repetitive Pattern SetBRP2 BRP3 BBC1 Bert Bit CounterBBC2 BBC3 BEC1 Bert Error CounterBEC2 BEC3 Step Action Payload Error Insertion FunctionTransmit Error Insertion Setup Sequence Table Bits 0 to 3/Error Insertion Rate Select Bits ER0 to ER3 Error Rate Control RegisterER3 ER2 ER1 ER0 Error Rate ERC Error Insertion Examples Table Number Of Error RegistersValue Write Read NOE1 NOEL2 Number Of Errors Left RegisterNOEL1 Interleaved PCM BUS Operation Channel Interleave ModeFrame Interleave Mode IBS1 IBS0 BUS Size IbocDA0 Device Position DS21Q55 #1 Rser DS21Q55 #3 Rser IBO Example Figure Esib Group of Four DS21Q55s Figure Extended System Information BUS Esib Extended System Information Bus Control Register ESIBCR1B0h ESIBSEL2 ESIBSEL1 ESIBSEL0 BUS BIT Driven ESI4SEL2 ESI4SEL1 ESI4SEL0 Status Output T1 Mode E1 Mode ESI3SEL2 ESI3SEL1 ESI3SEL0 Status Output T1 Mode E1 ModeESIBCR2 B1h ESIB2 ESIB1ESIB3 ESIB4 BPCS1 BPCS0 Programmable Backplane Clock SynthesizerCCR2 CCR3 Fractional T1/E1 Support72h Tdatfmt Tgpcken Rdatfmt Rgpcken Jtag Functional Block Diagram Figure JTAG-BOUNDARY-SCAN Architecture and TEST-ACCESS Port Update-DR Test-Logic-ResetTAP Controller State Machine Run-Test-Idle Select-IR-Scan Update-IRCapture-IR Shift-IR TAP Controller State Diagram Figure Instruction Selected Register Instruction Codes Instruction RegisterInstruction Codes for Ieee 1149.1 Architecture Table Device ID Codes Table ID Code Structure TableMSB LSB Device BIT ID Boundary Scan Register Test RegistersBypass Register Identification Register Boundary Scan Control Bits Table BIT PIN Symbol Type Control BIT DescriptionRchblk Jtms Bpclk Jtclk Jtrst ESIBS0 ESIBS1 MUX Tsig Teso NXA Tdata NXA Tsysclk Tssync TchclkDvss Dvdd Esibrd Rsysclk Rsync RLOS/LOTC Receive Side ESF Timing Figure Rclk Rsysclk Rsysclk Rser Transmit Side D4 Timing Figure Transmit Side ESF Timing Figure Transmit Side Boundary Timing With Elastic Store Disabled Tsysclk TSER1 32.2 E1 Mode Receive Side Timing Figure Receive Side Boundary Timing With Elastic Store Disabled RSYNC2 Rmsync RSYNC3 Rchclk Rchblk 221 012103 Receive IBO Channel Interleave Mode Timing Figure Receive IBO Frame Interleave Mode Timing Figure TIMING, E1 Mode only Figure Transmit Side Timing Figure Tser LSB Si Tssync Tchclk Tchblk 228 012103 Transmit IBO Channel Interleave Mode Timing Figure Transmit IBO Frame Interleave Mode Timing Figure THETA-JA θJA vs Airflow Thermal CharacteristicsOperating Parameters Absolute Maximum Ratings Parameter Symbol MIN TYP MAX DC CharacteristicsRecommended DC Operating Conditions Capacitance Parameter Symbol MIN TYP MAX Units AC Timing Parameters and Diagrams Intel BUS Write Timing BTS = 0 / MUX = 1 Figure Intel BUS Read Timing BTS = 0 / MUX = 1 Figure Motorola BUS Timing BTS = 1 / MUX = 1 Figure 236 012103 Intel BUS Read Timing BTS = 0 / MUX = 0 Figure Motorola BUS Read Timing BTS = 1 / MUX = 0 Figure Parameter Symbol MIN TYP MAX Units Receive Side AC CharacteristicsAC CHARACTERISTICS-RECEIVE Side Receive Side Timing T1 Mode Figure Receive Side TIMING, Elastic Store Enabled T1 Mode Figure Receive Line Interface Timing Figure Parameter Symbol MIN Transmit AC CharacteristicsTYP E1 MAX Units Tsysclk = 8.192MHz Tsysclk = 16.384MHz Transmit Side TIMING, Elastic Store Enabled Figure Transmit Line Interface Timing Figure Mechanical Descriptions Product Preview DS21Q55 248 012103