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Maxim DS21Q55 specifications TSER1

Models: DS21Q55

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Product Preview			DS21Q55
TRANSMIT SIDE 2.048MHz BOUNDARY TIMING (With Elastic Store Enabled)
Figure 35-11
TSYSCLK
CHANNEL 31		CHANNEL 32	CHANNEL 1
TSER1	LSB MSB	LSB	F4
TSSYNC
CHANNEL 31		CHANNEL 32	CHANNEL 1

TSIG A B C/A D/B A B C/A D/B A

TCHCLK

TCHBLK2,3

NOTES:

1) TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored.

2) TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored).

3) TCHBLK is forced to one in the same channels as TSER is ignored (Note 1).

4)The F-bit position for the T1 frame is sampled and passed through the transmit side elastic store into

the MSB bit position of channel 1. (Normally the transmit side formatter overwrites the F-bit position unless the formatter is programmed to pass-through the F-bit position).

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012103

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Contents

Applications FeaturesOrdering Information DescriptionProduct Preview DS21Q55 Ansi General Feature HighlightsLine Interface Clock SynthesizerSystem Interface Framer/FormatterHdlc Controllers Test and DiagnosticsExtended System Information Bus Control PortProduct Preview DS21Q55 012103 Table of Contents Signaling Operation Error Count RegistersPER-CHANNEL Idle Code Generation Channel Blocking Registers170 149177 186Operating Parameters AC Timing Parameters and DiagramsMechanical Descriptions Document Revision History Block Diagram Figure Block DiagramPIN Function Description Transmit Side PinsTSYNCx Transmit Signaling InputTransmit Sync Input/OutputReceive Side Pins Receive Signaling Freeze Receive Signaling OutputRSYNCx Receive SyncINT Parallel Control Port PinsTstrst BTS MUXA7/ALEAS Jtag Test Access Port PinsJtrst JtmsLine Interface Pins Supply Pins Pinout DS21Q55 PIN Description Table PIN Symbol Type DescriptionDVSS4 DVSS3ESIBRD1 ESIBRD2RFSYNC3 RFSYNC2RFSYNC4 RLCLK1RSIGF4 RSIGF3RSYNC1 RSYNC2TLINK4 TLINK3TNEGI1 TNEGI2TVSS3 TVSS2TVSS4 AD1 Package DS21Q55 Pin DIAGRAM, 27mm BGARegister Map Parallel PortAddress Register Name Abbreviation IMR9 SR9Pcpr PCDR1RS2 RS1RS3 RS4TCBR4 TCBR3H1TC H1FCRFDLM2 RFDLM1Iboc RAFInformation Register Name Special PER-CHANNEL Register OperationPcpr Rsaoics Rsrcs Rfcs Brcs Thscs Peics Tfcs BtcsPCDR2 PCDR1PCDR3 PCDR4Programming Sequence Figure Programming ModelMaster Mode Register Power-Up SequenceTEST1 TEST0 Effect on Output Pins MstrregStatus Registers Interrupt HandlingInterrupt Information Registers Information RegistersIIR1 IIR2Clock MAP Figure Clock MAPTransmit Clock Source T1 Control Registers T1 FRAMER/FORMATTER Control RegistersT1RCR1 OOF2 OOF1 OUT of Frame CriteriaBit 5/Receive B8ZS Enable RB8ZS = B8ZS disabled Bit 1/Receive Japanese CRC6 Enable RJCBit 6/Receive Frame Mode Select RFM = D4 framing mode T1RCR2T1TCR1 T1TCR2 Bit 7/Transmit B8ZS Enable TB8ZS = B8ZS disabled06h TB8ZS TSLC96 Tzse FBCT2 FBCT1 TD4YM Tzbtsi TB7ZST1CCR1 Bit 2/Transmit Frame Mode Select TFM = D4 framing modeT1 Common Control Register 07hT1 Receive-Side Digital-Milliwatt Code Generation T1 Transmit TransparencyT1RDMR2 T1RDMR1T1RDMR3 INFO1 T1 Information RegisterInformation Register 10hAlarm SET Criteria Clear Criteria T1 Alarm Criteria TableYellow Alarm RAI E1 Control Registers E1 FRAMER/FORMATTER Control RegistersE1RCR1 E1RCR2 E1 SYNC/RESYNC Criteria Table34h RclaE1TCR1 Bit 1/Automatic AIS Generation Aais = disabled Bit 0/Automatic Remote Alarm Generation ARA = disabledBit 2/Automatic E-Bit Enable Aebe E1TCR2Automatic Alarm Generation INFO3 E1 Information RegistersINFO7 E1 Alarm Criteria Table CCR1 Common Control and Status RegistersTCSS1 TCSS0 Transmit Clock Source SR2 IDRIMR2 Bit 2/Receive Unframed All Ones Blue Alarm Condition RUA1Interrupt Mask Register 19h1Ah SR3Lspare LDN LUP Lotc Lorc V52LNK Rdma RRA IMR3 Bit 0/Receive Remote Alarm Condition RRA = interrupt masked1Bh Bit 2/V5.2 Link Detected Condition V52LNK1Ch SR4RSA1 RSA0 TMF TAF RMF Rcmf RAF Bit 2/Receive Multiframe Event RMFIMR4 IOCR1 11. I/O PIN Configuration OptionsIOCR2 Lbcr Loopback ConfigurationLoopback Control Register 4AhInformation PCLR1 Per-Channel LoopbackPCLR2 4Dh PCLR3PCLR4 4EhErcnt Error Count RegistersT1 Line Code Violation Counting Options Table Line Code Violation Count Register LcvcrE1 Line Code Violation Counting Options Table T1 OperationLine Code Violation Count Register LCVCR142h LCVCR2Path Code Violation Count Register Pcvcr Framing ModeT1 Path Code Violation Counting Arrangements Table Frames Out Of Sync Count Register Foscr Framing Mode Count MOS or F-BIT Errors What is CountedT1 Frames OUT of Sync Counting Arrangements Table ERCNT.1Information FOSCR1 Bit Counter Register EbcrFOSCR2 EBCR1Transmit DS0 Monitor Registers 14. DS0 Monitoring FunctionTDS0SEL TDS0MRDS0SEL Receive DS0 Monitor RegistersRDS0M Signaling Operation Hardware-Based Receive Signaling Processor-Based Receive SignalingReceive-Signaling Reinsertion at Rser Change Of StateReceive-Signaling Freeze Force Receive Signaling All OnesSignaling Control Register SigcrMSB LSB CH2-A CH2-B MSB LSBCH1-A CH1-B CH4-A CH4-BRS1 to RS16 Receive Signaling Registers E1 Mode, CAS Format60h to 6Fh CH9-A CH9-B CH9-C CH9-D RS6RSCSE1 RSCSE1 , RSCSE2 , RSCSE3 , RSCSE4RSCSE2 RSCSE3Processor-Based Transmit Signaling 15.2.1.2 E1 Mode 15.2.1.1 T1 ModeTime Slot Numbering Schemes Table Channel PhoneTS1 to TS16 Transmit Signaling Registers E1 Mode, CAS Format50h to 5Fh TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9Transmit Signaling Registers E1 Mode, CCS Format 50h to 5Bh Transmit Signaling Registers T1 Mode, ESF FormatTS2 CH6-A CH6-B TS1 CH4-A CH4-BTS3 CH8-A CH8-B TS4SSIE1 Software Signaling Insertion Enable Registers, E1 CAS ModeSSIE2 0Ah SSIE3Lcaw SSIE4Software Signaling Insertion Enable Registers, T1 Mode Hardware-Based Transmit Signaling Idle Code Array Address Mapping Table PER-CHANNEL Idle Code GenerationBits 0-5 of Iaar Register Maps to Channel Write Iaar = 40h Write Pcicr = 7Eh Idle Code Programming ExamplesPcicr IaarTCICE1 TCICE2Information TCICE4 TCICE3RCICE1 RCICE286h RCICE3RCICE4 87hRCBR1 Channel Blocking RegistersRCBR2 RCBR4 RCBR3TCBR1 TCBR28Eh TCBR3TCBR4 8FhElastic Stores Operation Escr Bit 0/Receive Elastic Store Enable ReseElastic Store Control Register 4Fh1Eh SR5Tesf Tesem Tslip Resf Resem Rslip IMR5Product Preview DS21Q55 109 012103 18.1.2 E1 Mode 18.1.1 T1 ModeReceive Side Minimum-Delay Mode Elastic Store Delay After Initialization TableTransmit Side Elastic Stores Initialization112 012103 CRC-4 Recalculate Method Figure 19. G.706 INT Ermediate CRC-4 Updating E1 Mode onlyTransmit BOC 20. T1 BIT Oriented Code BOC ControllerReceive BOC BOC Control Register Bocc37h Rboce RBR RBF1 RBF0 SbocC0h Receive FDL RegisterSR8 24hIMR8 Hardware Scheme Method Additional Sa and International Si BIT Operation E1 onlyInternal Register Scheme Based On Double-Frame Method Rnaf RAFTnaf TAFRSiAF Internal Register Scheme Based On CRC4 Multiframe MethodReceive Si Bits of the Align Frame C8hRRA Receive Sa4 Bits RSa4CBh RSa5Receive Sa6 Bits RSa6CDh RSa7Receive Sa8 Bits RSa8CFh Transmit Si Bits of the Align Frame TSiAFD2h TRA Transmit Sa4 Bits TSa4D5h TSa5Transmit Sa6 Bits TSa6D7h TSa7Transmit Sa8 Bits TSa8D9h Tsacr Basic Operation Details Hdlc ControllersHdlc Controller Registers Table H1TC, H2TC Hdlc ConfigurationHdlc #1 Transmit Control, Hdlc #2 Transmit Control 90h, A0hH1RC, H2RC Bit 0/Receive SS7 Fill In Signal Unit Delete RsfdHdlc #1 Receive Control, Hdlc #2 Receive Control 31h, 32hH1FC, H2FC Fifo ControlRFHWM2 RFHWM1 RFHWM0 Receive Fifo Watermark Bytes TFLWM2 TFLWM1 TFLWM0 Transmit Fifo Watermark BytesReceive Hdlc MappingRegister Channels H2RCS1, H2RCS2, H2RCS3, H2RCS496h, A6h H1RTSBS, H2RTSBSRCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE 97h, 98h, 99h, 9Ah A7h, A8h, A9h, AAh TransmitTHCS7 THCS6 THCS5 THCS4 THCS3 THCS2 THCS1 THCS0 9Bh, Abh H1TTSBS, H2TTSBSTCB8SE TCB7SE TCB6SE TCB5SE TCB4SE TCB3SE TCB2SE TCB1SE Hdlc #1 Status Register Hdlc #2 Status Register SR6, SR720h, 22h Tmend RPE RPS Rhwm RNE Tlwm TNFIMR6, IMR7 PS2 PS1 PS0 Packet Status INFO5, INFO6INFO4 Receive Packet Bytes Available Fifo InformationH1TFBA, H2TFBA H1RPBA, H2RPBAH1TF, H2TF 22.3.5H1RF, H2RF Receive Hdlc Code Example Legacy FDL Support T1 ModeReceive Section RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0 RfdlRFDLM1, RFDLM2 Transmit Section 22.6 D4/SLC-96 OperationTfdl Transmit FDL RegisterBasic Network Connections Figure Line Interface Unit LIULIU Receiver LIU OperationMonitor Mode Receive G.703 Synchronization Signal E1 ModeTypical Monitor Application Figure Transmit G.703 Synchronization Signal E1 Mode Transmit BPV Error InsertionLIU Transmitter Transmit Short-Circuit Detector/LimiterCMI Code Mark Inversion Option Mclk PrescalerCMI Coding Figure LIC1 23.7 LIU Control RegistersApplication Return Loss E1 ModeTlbc Network Mode GC5 GC4 GC3 GC2 GC1 GC0Transmit Line Build-Out Control 7Dh79h LIC2ETS Lirst Ibpv TUA1 Jamux Scld Clds Bit 7/E1/T1 Select ETSMM1 MM0 LIC3TT1 TT0 Internal Transmit Termination Configuration RT1 RT0 Internal Receive Termination ConfigurationLIC4 MPS1 MPS0 Jamux LIC2.3RL3 RL2 RL1 RL0 INFO2CCR4 SR1 Ilut Timer Rscos16h Lrcl Tcle Tocd LolitcIMR1 Timer Rscos17h 1µF Recommended Circuits Basic Interface FigureProtected Interface Using Internal Receive Termination Specification Recommended Value Component Specifications Transformer Specifications TableT1 Transmit Pulse Template Figure E1 Transmit Pulse Template FigureJitter Tolerance E1 Mode Figure Jitter Tolerance T1 Mode FigureJitter Attenuation E1 Mode Figure Jitter Attenuation T1 Mode FigureProgrammable IN-BAND Loop Code Generation and Detection RDN2 RDN1 RDN0 IbccRUP2 RUP1 RUP0 TC1 TC0Transmit Code Definition Register TCD1B7h TCD2RUPCD2 RUPCD1RDNCD1 Rscc RDNCD2RSC2 RSC1 RSC0 Receive -Spare Code Definition Register RSCD1BEh RSCD2Bert Function BC1 Bert Register DescriptionPS2 PS1 PS0 Pattern Definition BC2 EIB2 EIB1 EIB0 Error Rate InsertedE1h Length BitsBIC Bit 0/BERT Enable Berten = Bert disabledBER T Interface Control Register EAh26h SR9Bbed Bbco BEC0 BRA1 BRA0 Brlos Bsync Bawc IMR9BRP1 Bert Repetitive Pattern SetBRP2 BRP3BBC1 Bert Bit CounterBBC2 BBC3BEC1 Bert Error CounterBEC2 BEC3Transmit Error Insertion Setup Sequence Table Payload Error Insertion FunctionStep Action Bits 0 to 3/Error Insertion Rate Select Bits ER0 to ER3 Error Rate Control RegisterER3 ER2 ER1 ER0 Error Rate ERCError Insertion Examples Table Number Of Error RegistersValue Write Read NOE1NOEL1 Number Of Errors Left RegisterNOEL2 Frame Interleave Mode Channel Interleave ModeInterleaved PCM BUS Operation DA0 Device Position IbocIBS1 IBS0 BUS Size DS21Q55 #1 Rser DS21Q55 #3 Rser IBO Example FigureEsib Group of Four DS21Q55s Figure Extended System Information BUS EsibExtended System Information Bus Control Register ESIBCR1B0h ESIBSEL2 ESIBSEL1 ESIBSEL0 BUS BIT DrivenESI4SEL2 ESI4SEL1 ESI4SEL0 Status Output T1 Mode E1 Mode ESI3SEL2 ESI3SEL1 ESI3SEL0 Status Output T1 Mode E1 ModeESIBCR2 B1hESIB2 ESIB1ESIB3 ESIB4CCR2 Programmable Backplane Clock SynthesizerBPCS1 BPCS0 CCR3 Fractional T1/E1 Support72h Tdatfmt Tgpcken Rdatfmt RgpckenJtag Functional Block Diagram Figure JTAG-BOUNDARY-SCAN Architecture and TEST-ACCESS PortUpdate-DR Test-Logic-ResetTAP Controller State Machine Run-Test-IdleSelect-IR-Scan Update-IRCapture-IR Shift-IRTAP Controller State Diagram Figure Instruction Codes for Ieee 1149.1 Architecture Table Instruction RegisterInstruction Selected Register Instruction Codes Device ID Codes Table ID Code Structure TableMSB LSB Device BIT IDBoundary Scan Register Test RegistersBypass Register Identification RegisterBoundary Scan Control Bits Table BIT PIN Symbol Type Control BIT DescriptionRchblk Jtms Bpclk Jtclk Jtrst ESIBS0ESIBS1 MUX Tsig Teso NXA Tdata NXA Tsysclk Tssync TchclkDvss Dvdd EsibrdRsysclk Rsync RLOS/LOTCReceive Side ESF Timing Figure Rclk Rsysclk Rsysclk Rser Transmit Side D4 Timing Figure Transmit Side ESF Timing Figure Transmit Side Boundary Timing With Elastic Store Disabled Tsysclk TSER1 32.2 E1 Mode Receive Side Timing Figure Receive Side Boundary Timing With Elastic Store Disabled RSYNC2 Rmsync RSYNC3 Rchclk Rchblk 221 012103 Receive IBO Channel Interleave Mode Timing Figure Receive IBO Frame Interleave Mode Timing Figure TIMING, E1 Mode only Figure Transmit Side Timing Figure Tser LSB Si Tssync Tchclk Tchblk 228 012103 Transmit IBO Channel Interleave Mode Timing Figure Transmit IBO Frame Interleave Mode Timing Figure Operating Parameters Absolute Maximum Ratings Thermal CharacteristicsTHETA-JA θJA vs Airflow Parameter Symbol MIN TYP MAX DC CharacteristicsRecommended DC Operating Conditions CapacitanceParameter Symbol MIN TYP MAX Units AC Timing Parameters and DiagramsIntel BUS Write Timing BTS = 0 / MUX = 1 Figure Intel BUS Read Timing BTS = 0 / MUX = 1 FigureMotorola BUS Timing BTS = 1 / MUX = 1 Figure 236 012103 Intel BUS Read Timing BTS = 0 / MUX = 0 Figure Motorola BUS Read Timing BTS = 1 / MUX = 0 Figure AC CHARACTERISTICS-RECEIVE Side Receive Side AC CharacteristicsParameter Symbol MIN TYP MAX Units Receive Side Timing T1 Mode Figure Receive Side TIMING, Elastic Store Enabled T1 Mode Figure Receive Line Interface Timing Figure Parameter Symbol MIN Transmit AC CharacteristicsTYP E1 MAX UnitsTsysclk = 8.192MHz Tsysclk = 16.384MHz Transmit Side TIMING, Elastic Store Enabled Figure Transmit Line Interface Timing Figure Mechanical Descriptions Product Preview DS21Q55 248 012103

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TSYSCLK

TSER1

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