Maxim specifications Package DS21Q55 Pin DIAGRAM, 27mm BGA, AD1

Product Preview DS21Q55

3.9 Package

DS21Q55 Pin DIAGRAM, 27mm BGA Figure 5 -1

The diagram shown below is the lead pattern that will be placed on the target PCB. This is the same pattern that would be seen as viewed from the top.

	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20
A	rnegi	rfsync	rlink	rclki	dvss	esibs1	tclko	tposi	dvdd	tsig	tsysclk	rlclk	rlink	cs	rclki	rposo	dvss	tchclk	tsysclk	dvss
	3	3	3	3	3	3	3	3	3	3	3	2	2	2*	2	2	2	2	2	2
B	rposo	rposi	dvdd	rclko	cs	dvdd	dvss	tchclk	dvss	tclk	dvss	dvdd	rclk	rposi	rnego	rsig	esibs1	tssync	tclk	tnego
	3	3	3	3	3*	3	3	3	3	3	2	2	2	2	2	2	2	2	2	2
C	rsig	rnego	eisb rd	dvdd	tvss	tlink	tsync	tclki	tposo	tser	tchblk	dvdd	eisbrd	rclko	rsigf	dvdd	tser	tsig	tposo	tposi
	3	3	3	3	3	3	3	3	3	3	3	2	2	2	2	2	2	2	2	2
D	rsync	rsigf	rlclk	rvss	rvss	tlclk	esibs0	tnegi	tnego	tssync	tvdd	rsync	rnegi	rchclk	rser	rmsync	rfsync	dvdd	tclki	tsync
	3	3	3	3	3	3	3	3	3	3	3	2	2	2	2	2	2	2	2	2
E	rlos	rser	rclk	rvdd													rlos	tclko	tlink	tlclk
	3	3	3	3													2	2	2	2
F	rlclk	rmsync	rchclk	bpclk													rsysclk	esibs0	tnegi	tchblk
	1	3	3	3													2	2	2	2
G	rsync	rlink	rsysclk	rchblk													rchblk	tvss	tvdd	dvdd
	1	1	3	3													2	2	2	4
H	rsysclk	rlos	dvss	a5													bpclk	NC	rvss	dvss
	1	1	1														2		2	4
J	rchclk	rser	dvdd	eisbrd													rvdd	rvss	D1/	esibs1
	1	1	1	1													2	2	AD1	4
K	rsigf	liuc	wr*	rfsync													cs	rlclk	tssync	tser
	1			1													4*	4	4	4
L	rmsync	rsig	rnego	rposo													A1	tchclk	tsig	dvss
	1	1	1	1														4	4	4
M	bpclk	rchblk	rclko	rclki													dvdd	rclk	tclk	dvdd
	1	1	1	1													4	4	4	4
N	jtdi	rd*	rclk	dvdd													dvss	tsys	tposo	tnego
			1	1													4	clk4	4	4
P	rvdd	bts	cs	A7/AL													rnegi	dvdd	tclko	tclki
	1		1*	E(AS)													4	4	4	4
R	tnegi	rvss	rnegi	rposI													rclki	tsync	tposi	tnegi
	1	1	1	1													4	4	4	4
T	mclk	rvss	tnego	A3													rclko	tlclk	tlink	esibs0
	1	1	1														4	4	4	4
U	int*	dvdd	A0	D7/	D5/	dvss	D3/	A6	D4/	mux	D0/	rlink	eisbrd	rchclk	rposo	tstrst	rnego	tvss	tvdd	tchblk
		1		AD7	AD5	1	AD3		AD4		AD0	4	4	4	4		4	4	4	4
V	tsync	A2	tlclk	D6/	dvdd	tclki	tposo	A4	esibs1	tchclk	rlos	rsync	bpclk	rfsync	rposi	rsigf	NC	jtrst*	jtdo	rvss
	1		1	AD6	1	1	1		1	1	4	4	4	4	4	4				4
W	tchblk	tvdd	tposi	tvss	tlink	esibs0	tclko	dvss	tser	tsig	tsysclk	tssync	jtms	rsysclk	D2/	rmsync	rser	rvdd	rvss	mclk
	1	1	1	1	1	1	1	1	1	1	1	1		4	AD2	4	4	4	4	2
Y	ttip	tring	ttip	tring	ttip	tring	ttip	tring	tclk	rtip	rring	rchblk	rtip	rring	jtclk	rtip	rring	rsig	rtip	rring
	1	1	2	2	3	3	4	4	1	1	1	4	2	2		3	3	4	4	4

NOTE: Locations C3, C13, J4, and U13 are used for the Extended System Information Bus (ESIB). These pin locations on the DS21Q352, DS21Q354, DS21Q552, and DS21Q554 are connected to ground. When replacing a DS21Qx5y with a DS21Q55B, these signals should be routed to control logic in order to gain access to the ESIB. If these pins remain connected to ground, the ESIB function will be disabled.

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