Maxim DS21Q55 DVSS3, DVSS4, ESIBRD1, ESIBRD2, ESIBRD3, ESIBRD4, ESIBS01, ESIBS02, ESIBS03, Int

Product Preview					DS21Q55
	PIN	SYMBOL	TYPE	DESCRIPTION
	A20	DVSS2	–	Digital Signal Ground.
	B11	DVSS2	–	Digital Signal Ground.
	A5	DVSS3	–	Digital Signal Ground.
	B7	DVSS3	–	Digital Signal Ground.
	B9	DVSS3	–	Digital Signal Ground.
	H20	DVSS4	–	Digital Signal Ground
	L20	DVSS4	–	Digital Signal Ground
	N17	DVSS4	–	Digital Signal Ground
	J4	ESIBRD1	–	Extended System Information Bus Read, Transceiver # 1.
	C13	ESIBRD2	–	Extended System Information Bus Read, Transceiver # 2.
	C3	ESIBRD3	–	Extended System Information Bus Read, Transceiver # 3.
	U13	ESIBRD4	–	Extended System Information Bus Read, Transceiver # 4.
	W6	ESIBS0_1	I/O	Extended System Information Bus 0, Transceiver # 1.
	F18	ESIBS0_2	I/O	Extended System Information Bus 0, Transceiver # 2.
	D7	ESIBS0_3	I/O	Extended System Information Bus 0, Transceiver # 3.
	T20	ESIBS0_4	I/O	Extended System Information Bus 0, Transceiver # 4.
	V9	ESIBS1_1	I/O	Extended System Information Bus 1, Transceiver # 1.
	B17	ESIBS1_2	I/O	Extended System Information Bus 1, Transceiver # 2.
	A6	ESIBS1_3	I/O	Extended System Information Bus 1, Transceiver # 3.
	J20	ESIBS1_4	I/O	Extended System Information Bus 1, Transceiver # 4.
	U1	INT*	O	Interrupt.
	Y15	JTCLK	I	JTAG Clock.
	N1	JTDI	I	JTAG Data Input, Transceiver #1
	V19	JTDO	O	JTAG Data Output. Transceiver #4
	W13	JTMS	I	JTAG Test Mode Select.
	V18	JTRST*	I	JTAG Reset.
	K2	LIUC	I	Line Interface Connect.
	T1	MCLK1	I	Master Clock, Transceiver #1 and, Transceiver #3.
	W20	MCLK2	I	Master Clock, Transceiver #2 and, Transceiver #4.
	U10	MUX	I	Mux Bus Select.
	M2	RCHBLK1	O	Receive Channel Block, Transceiver #1.
	G17	RCHBLK2	O	Receive Channel Block, Transceiver #2.
	G4	RCHBLK3	O	Receive Channel Block, Transceiver #3.
	Y12	RCHBLK4	O	Receive Channel Block, Transceiver #4.
	J1	RCHCLK1	O	Receive Channel Clock, Transceiver #1.
	D14	RCHCLK2	O	Receive Channel Clock, Transceiver #2.
	F3	RCHCLK3	O	Receive Channel Clock, Transceiver #3.
	U14	RCHCLK4	O	Receive Channel Clock, Transceiver #4.
	N3	RCLK1	O	Receive Clock Output from the Framer, Transceiver #1.
	B13	RCLK2	O	Receive Clock Output from the Framer, Transceiver #2.
	E3	RCLK3	O	Receive Clock Output from the Framer, Transceiver #3.
	M18	RCLK4	O	Receive Clock Output from the Framer, Transceiver #4.
	M4	RCLKI1	I	Receive Clock Input for the LIU, Transceiver #1.
	A15	RCLKI2	I	Receive Clock Input for the LIU, Transceiver #2.
	A4	RCLKI3	I	Receive Clock Input for the LIU, Transceiver #3.
	R17	RCLKI4	I	Receive Clock Input for the LIU, Transceiver #4.
	M3	RCLKO1	O	Receive Clock Output from the LIU, Transceiver #1.
	C14	RCLKO2	O	Receive Clock Output from the LIU, Transceiver #2.
	B4	RCLKO3	O	Receive Clock Output from the LIU, Transceiver #3.
	T17	RCLKO4	O	Receive Clock Output from the LIU, Transceiver #4.
	N2	RD*(DS*)	I	Read Input (Data Strobe)
	K4	RFSYNC1	O	Receive Frame Sync (before the receive elastic store), Transceiver
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