Maxim DS21Q55 specifications Framer/Formatter, System Interface

Product Preview DS21Q55

§Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation

§Can be placed in either the receive or transmit path or disabled

§Limit trip indication

1.1.5 Framer/Formatter

§Fully independent transmit and receive functionality

§Full receive- and transmit-path transparency

§T1 framing formats include D4 (SLC-96) and ESF

§Detailed alarm- and status-reporting with optional interrupt support

§Large path- and line-error counters for:

−T1 – BPV, CV, CRC6, and framing bit errors

−E1 – BPV, CV, CRC4, E-bit, and frame alignment errors

−Timed or manual update modes

§DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths

−User-defined

− Digital milliwatt

§ ANSI T1.403-1998 support

§ E1ETS 300 011 RAI generation § G.965 V5.2 link detect

§Ability to monitor one DS0 channel in both the transmit and receive paths

§ In-band repeating-pattern generators and detectors − Three independent generators and detectors

− Patterns from 1 bit to 8 bits or 16 bits in length

§RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state

§ Flexible signaling support

− Software- or hardware-based

−Interrupt generated on change of signaling data

−Receive-signaling freeze on loss of sync, carrier loss, or frame slip

§Addition of hardware pins to indicate carrier loss and signaling freeze

§Automatic RAI generation to ETS 300 011 specifications

§ Expanded access to Sa and Si bits

§Option to extend carrier- loss criteria to a 1ms period as per ETS 300 233

§ Japanese J1 support

−Ability to calculate and check CRC6 according to the Japanese standard

−Ability to generate yellow alarm according to the Japanese standard

1.1.6 System Interface

§Dual two- frame, independent receive and transmit elastic stores

−Independent control and clocking

−Controlled-slip capability with status

−Minimum-delay mode supported

§Maximum 16.384MHz backplane burst rate

§Supports T1 to CEPT (E1) conversion

§Programmable output clocks for fractional T1, E1, H0, and H12 applicatio ns

§Interleaving PCM bus operation

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