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Maxim DS21Q55 specifications 149, 170, 177, 186, 190, 193, 197, 198, 199, 208

Models: DS21Q55

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Product Preview					DS21Q55
	22.3.4 Receive Packet Bytes Available				144
	22.3.5		HDLC FIFOS		145
22.4		RECEIVE HDLC CODE EXAMPLE			146
22.5		LEGACY FDL SUPPORT (T1 MODE)			146
	22.5.1		Receive Section		146
	22.5.2		Transmit Section		148
22.6		D4/SLC– 96 OPERATION			148
23.	LINE INTERFACE UNIT (LIU)				149
23.1		LIU OPERATION			150
23.2		LIU RECEIVER			150
	23.2.1		Receive Level Indicator	Error! Bookmark not defined.
	23.2.2 Receive G.703 Synchronization Signal (E1 Mode)				151
	23.2.3		Monitor Mode		151
23.3		LIU TRANSMITTER			152
	23.3.1		Transmit Short-Circuit Detector/Limiter		152
	23.3.2		Transmit Open-Circuit Detector		152
	23.3.3 Transmit BPV Error Insertion				152
	23.3.4 Transmit G.703 Synchronization Signal (E1 Mode)				152
23.4		MCLK PRESCALER			153
23.5		JITTER ATTENUATOR			153
23.6		CMI (CODE MARK INVERSION) OPTION			153
23.7		LIU CONTROL REGISTERS			154
23.8		RECOMMENDED CIRCUITS			164
23.9		COMPONENT SPECIFICATIONS			166
24.	PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION				................170
25.		BERT FUNCTION			177
25.1		BERT REGISTER DESCRIPTION			178
25.2		BERT REPETITIVE PATTERN SET			183
25.3		BERT BIT COUNTER			184
25.4		BERT ERROR COUNTER			185
26.	PAYLOAD ERROR INSERTION FUNCTION				186
26.1		NUMBER OF ERROR REGISTERS			188
	26.1.1 Number Of Errors Left Register				189
27.	INTERLEAVED PCM BUS OPERATION				190
27.1		CHANNEL INTERLEAVE MODE			190
27.2		FRAME INTERLEAVE MODE			190
28.	EXTENDED SYSTEM INFORMATION BUS (ESIB)				193
29.	PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER				197
30.		FRACTIONAL T1/E1 SUPPORT			198
31.		JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT			199
31.1		INSTRUCTION REGISTER			203
31.2		TEST REGISTERS			205
31.3		BOUNDARY SCAN REGISTER			205
31.4		BYPASS REGISTER			205
31.5		IDENTIFICATION REGISTER			205
32.		FUNCTIONAL TIMING DI AGRAMS			208
32.1		T1 MODE			208
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Maxim DS21Q55 specifications 149, 170, 177, 186, 190, 193, 197, 198, 199, 208

Contents

Ordering Information FeaturesApplications DescriptionProduct Preview DS21Q55 Ansi Line Interface Feature HighlightsGeneral Clock SynthesizerFramer/Formatter System InterfaceExtended System Information Bus Test and DiagnosticsHdlc Controllers Control PortProduct Preview DS21Q55 012103 Table of Contents PER-CHANNEL Idle Code Generation Error Count RegistersSignaling Operation Channel Blocking Registers177 149170 186Operating Parameters AC Timing Parameters and DiagramsMechanical Descriptions Document Revision History Block Diagram Block Diagram FigureTransmit Side Pins PIN Function DescriptionTransmit Sync Transmit Signaling InputTSYNCx Input/OutputReceive Side Pins RSYNCx Receive Signaling OutputReceive Signaling Freeze Receive SyncINT Parallel Control Port PinsTstrst MUX BTSJtrst Jtag Test Access Port PinsA7/ALEAS JtmsLine Interface Pins Supply Pins PIN Symbol Type Description Pinout DS21Q55 PIN Description TableESIBRD1 DVSS3DVSS4 ESIBRD2RFSYNC4 RFSYNC2RFSYNC3 RLCLK1RSYNC1 RSIGF3RSIGF4 RSYNC2TNEGI1 TLINK3TLINK4 TNEGI2TVSS3 TVSS2TVSS4 Package DS21Q55 Pin DIAGRAM, 27mm BGA AD1Register Map Parallel PortAddress Register Name Abbreviation Pcpr SR9IMR9 PCDR1RS3 RS1RS2 RS4H1TC TCBR3TCBR4 H1FCIboc RFDLM1RFDLM2 RAFInformation Pcpr Special PER-CHANNEL Register OperationRegister Name Rsaoics Rsrcs Rfcs Brcs Thscs Peics Tfcs BtcsPCDR3 PCDR1PCDR2 PCDR4Programming Model Programming Sequence FigureTEST1 TEST0 Effect on Output Pins Power-Up SequenceMaster Mode Register MstrregInterrupt Handling Status RegistersIIR1 Information RegistersInterrupt Information Registers IIR2Clock MAP Figure Clock MAPTransmit Clock Source T1RCR1 T1 FRAMER/FORMATTER Control RegistersT1 Control Registers OOF2 OOF1 OUT of Frame CriteriaBit 6/Receive Frame Mode Select RFM = D4 framing mode Bit 1/Receive Japanese CRC6 Enable RJCBit 5/Receive B8ZS Enable RB8ZS = B8ZS disabled T1RCR2T1TCR1 06h Bit 7/Transmit B8ZS Enable TB8ZS = B8ZS disabledT1TCR2 TB8ZS TSLC96 Tzse FBCT2 FBCT1 TD4YM Tzbtsi TB7ZST1 Common Control Register Bit 2/Transmit Frame Mode Select TFM = D4 framing modeT1CCR1 07hT1 Transmit Transparency T1 Receive-Side Digital-Milliwatt Code GenerationT1RDMR2 T1RDMR1T1RDMR3 Information Register T1 Information RegisterINFO1 10hAlarm SET Criteria Clear Criteria T1 Alarm Criteria TableYellow Alarm RAI E1 Control Registers E1 FRAMER/FORMATTER Control RegistersE1RCR1 34h E1 SYNC/RESYNC Criteria TableE1RCR2 RclaE1TCR1 Bit 2/Automatic E-Bit Enable Aebe Bit 0/Automatic Remote Alarm Generation ARA = disabledBit 1/Automatic AIS Generation Aais = disabled E1TCR2Automatic Alarm Generation INFO3 E1 Information RegistersINFO7 E1 Alarm Criteria Table CCR1 Common Control and Status RegistersTCSS1 TCSS0 Transmit Clock Source IDR SR2Interrupt Mask Register Bit 2/Receive Unframed All Ones Blue Alarm Condition RUA1IMR2 19h1Ah SR3Lspare LDN LUP Lotc Lorc V52LNK Rdma RRA 1Bh Bit 0/Receive Remote Alarm Condition RRA = interrupt maskedIMR3 Bit 2/V5.2 Link Detected Condition V52LNKRSA1 RSA0 TMF TAF RMF Rcmf RAF SR41Ch Bit 2/Receive Multiframe Event RMFIMR4 11. I/O PIN Configuration Options IOCR1IOCR2 Loopback Control Register Loopback ConfigurationLbcr 4AhInformation PCLR1 Per-Channel LoopbackPCLR2 PCLR4 PCLR34Dh 4EhError Count Registers ErcntE1 Line Code Violation Counting Options Table Line Code Violation Count Register LcvcrT1 Line Code Violation Counting Options Table T1 Operation42h LCVCR1Line Code Violation Count Register LCVCR2Path Code Violation Count Register Pcvcr Framing ModeT1 Path Code Violation Counting Arrangements Table T1 Frames OUT of Sync Counting Arrangements Table Framing Mode Count MOS or F-BIT Errors What is CountedFrames Out Of Sync Count Register Foscr ERCNT.1Information FOSCR2 Bit Counter Register EbcrFOSCR1 EBCR1TDS0SEL 14. DS0 Monitoring FunctionTransmit DS0 Monitor Registers TDS0MRDS0SEL Receive DS0 Monitor RegistersRDS0M Signaling Operation Receive-Signaling Reinsertion at Rser Processor-Based Receive SignalingHardware-Based Receive Signaling Change Of StateSignaling Control Register Force Receive Signaling All OnesReceive-Signaling Freeze SigcrCH1-A CH1-B MSB LSBMSB LSB CH2-A CH2-B CH4-A CH4-B60h to 6Fh Receive Signaling Registers E1 Mode, CAS FormatRS1 to RS16 CH9-A CH9-B CH9-C CH9-D RS6RSCSE2 RSCSE1 , RSCSE2 , RSCSE3 , RSCSE4RSCSE1 RSCSE3Processor-Based Transmit Signaling Time Slot Numbering Schemes Table 15.2.1.1 T1 Mode15.2.1.2 E1 Mode Channel Phone50h to 5Fh Transmit Signaling Registers E1 Mode, CAS FormatTS1 to TS16 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9Transmit Signaling Registers E1 Mode, CCS Format Transmit Signaling Registers T1 Mode, ESF Format 50h to 5BhTS3 CH8-A CH8-B TS1 CH4-A CH4-BTS2 CH6-A CH6-B TS4SSIE1 Software Signaling Insertion Enable Registers, E1 CAS ModeSSIE2 Lcaw SSIE30Ah SSIE4Software Signaling Insertion Enable Registers, T1 Mode Hardware-Based Transmit Signaling Idle Code Array Address Mapping Table PER-CHANNEL Idle Code GenerationBits 0-5 of Iaar Register Maps to Channel Idle Code Programming Examples Write Iaar = 40h Write Pcicr = 7EhTCICE1 IaarPcicr TCICE2Information RCICE1 TCICE3TCICE4 RCICE2RCICE4 RCICE386h 87hRCBR1 Channel Blocking RegistersRCBR2 TCBR1 RCBR3RCBR4 TCBR2TCBR4 TCBR38Eh 8FhElastic Stores Operation Elastic Store Control Register Bit 0/Receive Elastic Store Enable ReseEscr 4FhTesf Tesem Tslip Resf Resem Rslip SR51Eh IMR5Product Preview DS21Q55 109 012103 18.1.2 E1 Mode 18.1.1 T1 ModeReceive Side Transmit Side Elastic Store Delay After Initialization TableMinimum-Delay Mode Elastic Stores Initialization112 012103 19. G.706 INT Ermediate CRC-4 Updating E1 Mode only CRC-4 Recalculate Method FigureTransmit BOC 20. T1 BIT Oriented Code BOC ControllerReceive BOC 37h BoccBOC Control Register Rboce RBR RBF1 RBF0 SbocSR8 Receive FDL RegisterC0h 24hIMR8 Hardware Scheme Method Additional Sa and International Si BIT Operation E1 onlyInternal Register Scheme Based On Double-Frame Method RAF RnafTAF TnafReceive Si Bits of the Align Frame Internal Register Scheme Based On CRC4 Multiframe MethodRSiAF C8hRRA CBh RSa4Receive Sa4 Bits RSa5CDh RSa6Receive Sa6 Bits RSa7Receive Sa8 Bits RSa8CFh Transmit Si Bits of the Align Frame TSiAFD2h TRA D5h TSa4Transmit Sa4 Bits TSa5D7h TSa6Transmit Sa6 Bits TSa7Transmit Sa8 Bits TSa8D9h Tsacr Hdlc Controllers Basic Operation DetailsHdlc Controller Registers Table Hdlc #1 Transmit Control, Hdlc #2 Transmit Control Hdlc ConfigurationH1TC, H2TC 90h, A0hHdlc #1 Receive Control, Hdlc #2 Receive Control Bit 0/Receive SS7 Fill In Signal Unit Delete RsfdH1RC, H2RC 31h, 32hRFHWM2 RFHWM1 RFHWM0 Receive Fifo Watermark Bytes Fifo ControlH1FC, H2FC TFLWM2 TFLWM1 TFLWM0 Transmit Fifo Watermark BytesRegister Channels Hdlc MappingReceive H2RCS1, H2RCS2, H2RCS3, H2RCS496h, A6h H1RTSBS, H2RTSBSRCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE 97h, 98h, 99h, 9Ah A7h, A8h, A9h, AAh TransmitTHCS7 THCS6 THCS5 THCS4 THCS3 THCS2 THCS1 THCS0 9Bh, Abh H1TTSBS, H2TTSBSTCB8SE TCB7SE TCB6SE TCB5SE TCB4SE TCB3SE TCB2SE TCB1SE 20h, 22h SR6, SR7Hdlc #1 Status Register Hdlc #2 Status Register Tmend RPE RPS Rhwm RNE Tlwm TNFIMR6, IMR7 PS2 PS1 PS0 Packet Status INFO5, INFO6INFO4 H1TFBA, H2TFBA Fifo InformationReceive Packet Bytes Available H1RPBA, H2RPBAH1TF, H2TF 22.3.5H1RF, H2RF Receive Hdlc Code Example Legacy FDL Support T1 ModeReceive Section RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0 RfdlRFDLM1, RFDLM2 Tfdl 22.6 D4/SLC-96 OperationTransmit Section Transmit FDL RegisterLine Interface Unit LIU Basic Network Connections FigureLIU Operation LIU ReceiverMonitor Mode Receive G.703 Synchronization Signal E1 ModeTypical Monitor Application Figure LIU Transmitter Transmit BPV Error InsertionTransmit G.703 Synchronization Signal E1 Mode Transmit Short-Circuit Detector/LimiterCMI Code Mark Inversion Option Mclk PrescalerCMI Coding Figure 23.7 LIU Control Registers LIC1E1 Mode Application Return LossTransmit Line Build-Out Control Network Mode GC5 GC4 GC3 GC2 GC1 GC0Tlbc 7DhETS Lirst Ibpv TUA1 Jamux Scld Clds LIC279h Bit 7/E1/T1 Select ETSLIC3 MM1 MM0LIC4 RT1 RT0 Internal Receive Termination ConfigurationTT1 TT0 Internal Transmit Termination Configuration MPS1 MPS0 Jamux LIC2.3INFO2 RL3 RL2 RL1 RL0CCR4 16h Ilut Timer RscosSR1 Lrcl Tcle Tocd LolitcIMR1 Timer Rscos17h Recommended Circuits Basic Interface Figure 1µFProtected Interface Using Internal Receive Termination Component Specifications Transformer Specifications Table Specification Recommended ValueE1 Transmit Pulse Template Figure T1 Transmit Pulse Template FigureJitter Tolerance T1 Mode Figure Jitter Tolerance E1 Mode FigureJitter Attenuation T1 Mode Figure Jitter Attenuation E1 Mode FigureProgrammable IN-BAND Loop Code Generation and Detection RUP2 RUP1 RUP0 IbccRDN2 RDN1 RDN0 TC1 TC0B7h TCD1Transmit Code Definition Register TCD2RUPCD1 RUPCD2RDNCD1 Rscc RDNCD2RSC2 RSC1 RSC0 BEh RSCD1Receive -Spare Code Definition Register RSCD2Bert Function BC1 Bert Register DescriptionPS2 PS1 PS0 Pattern Definition E1h EIB2 EIB1 EIB0 Error Rate InsertedBC2 Length BitsBER T Interface Control Register Bit 0/BERT Enable Berten = Bert disabledBIC EAh26h SR9Bbed Bbco BEC0 BRA1 BRA0 Brlos Bsync IMR9 BawcBRP2 Bert Repetitive Pattern SetBRP1 BRP3BBC2 Bert Bit CounterBBC1 BBC3BEC2 Bert Error CounterBEC1 BEC3Transmit Error Insertion Setup Sequence Table Payload Error Insertion FunctionStep Action ER3 ER2 ER1 ER0 Error Rate Error Rate Control RegisterBits 0 to 3/Error Insertion Rate Select Bits ER0 to ER3 ERCValue Write Read Number Of Error RegistersError Insertion Examples Table NOE1NOEL1 Number Of Errors Left RegisterNOEL2 Frame Interleave Mode Channel Interleave ModeInterleaved PCM BUS Operation DA0 Device Position IbocIBS1 IBS0 BUS Size IBO Example Figure DS21Q55 #1 Rser DS21Q55 #3 RserExtended System Information BUS Esib Esib Group of Four DS21Q55s FigureB0h ESIBCR1Extended System Information Bus Control Register ESIBSEL2 ESIBSEL1 ESIBSEL0 BUS BIT DrivenESIBCR2 ESI3SEL2 ESI3SEL1 ESI3SEL0 Status Output T1 Mode E1 ModeESI4SEL2 ESI4SEL1 ESI4SEL0 Status Output T1 Mode E1 Mode B1hESIB3 ESIB1ESIB2 ESIB4CCR2 Programmable Backplane Clock SynthesizerBPCS1 BPCS0 72h Fractional T1/E1 SupportCCR3 Tdatfmt Tgpcken Rdatfmt RgpckenJTAG-BOUNDARY-SCAN Architecture and TEST-ACCESS Port Jtag Functional Block Diagram FigureTAP Controller State Machine Test-Logic-ResetUpdate-DR Run-Test-IdleCapture-IR Update-IRSelect-IR-Scan Shift-IRTAP Controller State Diagram Figure Instruction Codes for Ieee 1149.1 Architecture Table Instruction RegisterInstruction Selected Register Instruction Codes MSB LSB ID Code Structure TableDevice ID Codes Table Device BIT IDBypass Register Test RegistersBoundary Scan Register Identification RegisterRchblk Jtms Bpclk Jtclk Jtrst BIT PIN Symbol Type Control BIT DescriptionBoundary Scan Control Bits Table ESIBS0Dvss Dvdd Tsig Teso NXA Tdata NXA Tsysclk Tssync TchclkESIBS1 MUX EsibrdRsync RLOS/LOTC RsysclkReceive Side ESF Timing Figure Rclk Rsysclk Rsysclk Rser Transmit Side D4 Timing Figure Transmit Side ESF Timing Figure Transmit Side Boundary Timing With Elastic Store Disabled Tsysclk TSER1 32.2 E1 Mode Receive Side Timing Figure Receive Side Boundary Timing With Elastic Store Disabled RSYNC2 Rmsync RSYNC3 Rchclk Rchblk 221 012103 Receive IBO Channel Interleave Mode Timing Figure Receive IBO Frame Interleave Mode Timing Figure TIMING, E1 Mode only Figure Transmit Side Timing Figure Tser LSB Si Tssync Tchclk Tchblk 228 012103 Transmit IBO Channel Interleave Mode Timing Figure Transmit IBO Frame Interleave Mode Timing Figure Operating Parameters Absolute Maximum Ratings Thermal CharacteristicsTHETA-JA θJA vs Airflow Recommended DC Operating Conditions DC CharacteristicsParameter Symbol MIN TYP MAX CapacitanceAC Timing Parameters and Diagrams Parameter Symbol MIN TYP MAX UnitsIntel BUS Read Timing BTS = 0 / MUX = 1 Figure Intel BUS Write Timing BTS = 0 / MUX = 1 FigureMotorola BUS Timing BTS = 1 / MUX = 1 Figure 236 012103 Intel BUS Read Timing BTS = 0 / MUX = 0 Figure Motorola BUS Read Timing BTS = 1 / MUX = 0 Figure AC CHARACTERISTICS-RECEIVE Side Receive Side AC CharacteristicsParameter Symbol MIN TYP MAX Units Receive Side Timing T1 Mode Figure Receive Side TIMING, Elastic Store Enabled T1 Mode Figure Receive Line Interface Timing Figure TYP E1 Transmit AC CharacteristicsParameter Symbol MIN MAX UnitsTsysclk = 8.192MHz Tsysclk = 16.384MHz Transmit Side TIMING, Elastic Store Enabled Figure Transmit Line Interface Timing Figure Mechanical Descriptions Product Preview DS21Q55 248 012103