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DS21Q55

NOTES:

1)Jitter attenuator enabled in the receive path.

2)Jitter attenuator disabled or enabled in the transmit path.

3)RSYSCLK = 1.544MHz.

4)RSYSCLK = 2.048MHz.

5)RSYSCLK = 4.096MHz.

6)RSYSCLK = 8.192MHz.

7)RSYSCLK = 16.384MHz.

RECEIVE SIDE TIMING (T1 MODE) Figure 37-8

RCLK

 

 

 

 

 

tD1

 

RSER / RDATA / RSIG

F Bit

 

 

 

 

t D2

RCHCLK

 

 

 

 

 

t D2

RCHBLK

 

 

 

 

 

t D2

RFSYNC / RMSYNC

 

 

1

t D2

RSYN

 

 

 

 

C

 

 

t D2

 

 

2

RLCLK

 

 

 

 

 

tD1

RLINK

 

 

 

NOTES:

 

 

 

1)RSYNC is in the output mode.

2)Shown is RLINK/RLCLK in the ESF framing mode.

3)No relationship between RCHCLK and RCHBLK and other signals is implied.

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Maxim DS21Q55 specifications Receive Side Timing T1 Mode Figure