10 TROUBLESHOOTING

MELSEC-Q

10.1.4 Reading the data communication status (Transmission sequence status)

This section explains how to read the current status of the data communication using the MC protocol stored in the buffer memory.

When GX Configurator-SC is used, check the status using the "MC protocol monitor" screen (see Section 8.6.4).

When a transmission problem occurs, read operation is executed to check the status of the data communication using the MC protocol.

(1) Transmission sequence status storage area (address: 255H and 265H)

The status of data communication using the MC protocol is stored as a numerical value in buffer memory addresses 255H and 265H.

 

b15

to

b0

Buffer memory address 255H

 

0 to 9

 

(Information on the CH1 side)

265H

0 to 9

 

(Information on the CH2 side)

The following shows the correspondence between the numerical values in the transmission sequence status storage area and the data communication status.

Request from an external device

E

External N

device Q

Q series C24

Station number HL

Message wait

ACK

or

NAK

Request

to CPU

Response

 

from

"6" "1"..."6" is repeated afterward.

CPU

 

Stored

0

1

3

4

5

6

value

 

 

2

Values 7 to 9 are stored when "mode switching" or "initialization

of transmission sequence" is performed.

REMARK

When the target interface is not set to use the MC protocol, "0" is stored in the transmission sequence status storage area.

(2)Example of a program that reads from transmission sequence status storage area

The following shows an example of a program that reads from the transmission sequence status storage area.

(input/output signals X/Y00 to X/Y1F of the Q series C24) Example of FROM instruction

Read command

b15to

D00

D14

Reads the status of data communication on the CH1 side from address 255H.

Reads the status of data communication on the CH2 side from address 265H.

b0

The CH1 side is waiting to receive a command message, and is using non procedure or bidirectional protocol.

CH2 is accessing the PLC CPU upon reception of a command message.

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