3 SPECIFICATIONS
REMARK
(1) Confirmation of
The control signal status of DTR, DSR, RS, and CD can be confirmed during data communication by the
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| Buffer memory address | ||
Bit position | CH1 side |
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| CH2 side |
| 254H |
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| 264H |
b0 |
| RS |
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b1 |
| DSR |
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b2 |
| DTR |
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b3 |
| CD |
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b4 |
| CS | 1 | |
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b5 |
| RI |
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b6 to b15 |
| — |
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1 System area for QJ71C24
(2) Designation of RS and DTR signal status
When the Q series it turned on or off, the on and off states of the RS and DTR signals can be designated when the buffer memory of the RS and DTR signal
status designation area (address: 92H, 132H) for the corresponding bit is turned on or off by the RS signal or DTR signal. 
1 
2 
3
b15 | b3 | b2 | b1 | b0 |
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Buffer memory address 92H/132H |
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| 1/0 |
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| 1/0 [Default 0005H] | |
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System |
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| RS | 1:ON | ||
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| 0:OFF | |
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| DTR | |
1 The RS signal is controlled by the Q series C24 in the following cases. (Ignore setting contents.)
•When data is communicated with
•When communication time and the RS and CS signals are controlled by the modem function 
2 The DTR signal is controlled by the Q series C24 in the following cases. (Ignore setting
contents.)
•When the DTR and DSR signals are controlled
•When data is communicated by the modem function
3 After writing in the buffer memory, a lag of 0 to 20 ms occurs until it is reflected in the signal.
POINT
Be sure to control the RS and DTR signals with the Q series C24. Control of the RS and DTR signals by the user is a prime factor for data communication errors.
3.2.2
•Use a 15 m (49.21 ft.), or shorter, cable conforming to the
(Recommended cable)
7/0. 127 
P 
:
(Oki Electric Cable Co., Ltd)
3 - 5 | 3 - 5 |