Samsung KFKAGH6Q4M Pin Description, Multiplexed Address/Data bus, Register read cycles, Interrupt

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)	FLASH MEMORY
2.4 Pin Description

Pin Name

Type

Nameand Description

Host Interface

		Multiplexed Address/Data bus
		- Inputs for addresses during read operation, which are for addressing BufferRAM & Register.
ADQ15~ADQ0	I/O	- Inputs data during program and commands for all operations, outputs data during memory array/
		register read cycles.
		Data pins float to high-impedance when the chip is deselected or outputs are disabled.

				Interrupt
INT / INT1			O	Notifies the Host when a command is completed. After power-up, it is at hi-z condition. Once IOBE is set to 1, it does not float
				to hi-z condition even when CE is disabled or OE is disabled. Especially, only when reset(Cold, Warm, Hot, NAND Flash
				Core) command in DDP are issued, it operates as open drain output with internal resistor (~50Kohm). The INT is the interrupt
				for Single or DDP device. The INT1 is the interrupt for the first DDP device(KFN8GH6Q4M) in QDP(KFKAGH6Q4M)
INT2			O	Interrupt
				The INT2 is the interrupt for the second DDP device(KFN8GH6Q4M) in QDP(KFKAGH6Q4M)
RDY			O	Ready
				Indicates data valid in synchronous read modes and is activated while CE is low
				Clock
	CLK		I	CLK synchronizes the device to the system bus frequency in synchronous read mode.
				The first rising edge of CLK in conjunction with AVD low latches address input.
			I	Write Enable
		WE
				WE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge
				Address Valid Detect
				Indicates valid address presence on address inputs. During asynchronous read operation, all addresses are valid while	AVD
			I	is low, and during synchronous read operation, all addresses are latched on CLK’s rising edge while AVD is held low for one
	AVD			clock cycle.

>Low : for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge on CLK

>High : device ignores address inputs

Reset Pin

RP

I

When low,

RP

resets internal operation of Flex-MuxOneNAND.

RP

status is do not care during power-up

and bootloading. When high, RP level must be equivalent to Vcc-IO / Vccq level.

Chip Enable

/

I

CE-low activates internal control logic, and

CE

-high deselects the device, places it in standby state,

CE

CE1

and places DQ in Hi-Z.

The CE input enables device for Single or DDP .

The CE1 input enables the first DDP device(KFN8GH6Q4M) in QDP(KFKAGH6Q4M)

I

Chip Enable

CE2

The CE2 input enables the second DDP device(KFN8GH6Q4M) in QDP(KFKAGH6Q4M)

Output Enable

OE

I

OE-low enables the device’s output data buffers during a read cycle.

Power Supply

VCC-Core

Power for Flex-MuxOneNAND Core

/ Vcc

This is the power supply for Flex-MuxOneNAND Core.

VCC-IO

Power for Flex-MuxOneNAND I/O

This is the power supply for Flex-MuxOneNAND I/O

/ Vccq

Vcc-IO / Vccq is internally separated from Vcc-Core / Vcc.

VSS

Ground for Flex-MuxOneNAND

etc.

DNU

Do Not Use

Leave it disconnected. These pins are used for testing.

NC

No Connection

Lead is not internally connected.

NOTE :

Do not leave power supply(Vcc-Core/Vcc-IO, VSS) disconnected.

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