Cold Reset Timing | Samsung KFN8GH6Q4M, KFKAGH6Q4M, KFM4GH6Q4M

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)	FLASH MEMORY
6.15 Cold Reset Timing

POR triggering level

System Power

			1)	Bootcode - copy done
				Bootcode - copy done
	OneNAND	Sleep	Bootcode copy	Idle
	Operation	Sleep	Bootcode copy	Idle
	Operation
			2)
	RP
	INT		High-Z	3)
	INT			3)
	INT bit		0 (default)	1
	IOBE bit		0 (default)	1

INTpol bit

1 (default)

NOTE :

1)Bootcode copy operation starts 400us later than POR activation.

The system power should reach Vcc after POR triggering level(typ. 1.5V) within 400us for valid boot code data.

2)1KB Bootcode copy and internal update operation take 250us(estimated) from sector0 and 1/page0/block0 of NAND Flash array to BootRAM. Host can read Bootcode in BootRAM(1K bytes) after Bootcode copy completion.

3)INT register goes ‘Low’ to ‘High’ on the condition of ‘Bootcode-copy done’ and RP rising edge.

If RP goes ‘Low’ to ‘High’ before ‘Bootcode-copy done’, INT register goes to ‘Low’ to ‘High’ as soon as ‘Bootcode-copy done’

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Image 126

Samsung KFN8GH6Q4M, KFKAGH6Q4M, KFM4GH6Q4M warranty Cold Reset Timing

Contents

KFM4GH6Q4M KFN8GH6Q4M KFKAGH6Q4M Remark Initial issueRevision No History Draft Date Corrected errata Oct Ordering Information General Overview Device Performance Product FeaturesDevice Architecture System Hardware Detailed Product Description Definitions Pin Configuration 1 4Gb KFM4GH6Q4M / 8Gb KFN8GH6Q4M63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA4Gb 2 16Gb Product KFKAGH6Q4M TBD TOP VIEW, Balls Facing Down 63ball Fbga OneNAND Chip Register read cycles Pin DescriptionMultiplexed Address/Data bus Interrupt Internal Nand Array Memory Organization Block DiagramMemory Array Organization OTP Sector BlockMLCBlockSLC External BufferRAM Memory BootRAM 1KB DataRAM0 2KB DataRAM1 2KBBoot code Nand Array OTP Block Internal Nand Array Memory 0000h Memory MapBlock Block Address Size 256KB Block Block Address Block129 Block128Block160 Block161 Block238 00EEh Block240 00F0h Block289 0121h Block258 Block256Block288 0120h Block257 Block290 0122h Block259 Block353 0161h Block322 Block320Block352 0160h Block321 Block354 0162h Block323 Block385 Block384Block416 Block417 Block494 01EEh Block496 01F0h Block545 0221h Block514 Block512Block544 0220h Block513 Block546 0222h Block515 Block609 0261h Block578 Block576Block608 0260h Block577 Block610 0262h Block579 Block641 Block640Block672 Block673 Block750 02EEh Block752 02F0h Block801 0321h Block770 Block768Block800 0320h Block769 Block802 0322h Block771 Block865 0361h Block834 Block832Block864 0360h Block833 Block866 0362h Block835 Block897 Block896Block928 Block929 Block1006 03EEh Block1008 03F0h 256W Internal Memory Spare Area AssignmentArea Byte External Memory BufferRAM Address Map Division Address Size Usage Description External Memory Map Detail Information BootRAMMain areaBootRAMSpare area DataRAMMain area External Memory Spare Area Assignment Buf Word Byte 10054h 802Bh 10056h 802Ch 10058h 802Dh 10074h 803Bh 10076h 803Ch 10078h 803Dh4bit ECC parity values 8046h 1008Ch 8047h 1008Eh 10092h Managed by internal ECC logic DataS10090h BIBad block Information 10094h 804Bh 10096h 804Ch 10098h 804Dh Registers Register Address MapAddress Name Host Description Device ID Register F001h R Device ID DefaultManufacturer ID Register F000h R Device Identification Version ID Register F002h Data Buffer Size Register F003h RThis register is reserved for future use Boot Buffer Size Register F004h R Amount of Buffers Register F005h RTechnology Register F006h R Start Address1 Register F100h R/W Start Address2 Register F101h R/W11~15 Start Address3~7 Register F102h~F106h Start Address8 Register F107h R/W Start Buffer Register F200h R/W Sector allocation according to BSCCASE2 FSA=01 BSC = Sector allocation according to BSCCASE1 FSA=00 BSC =BSC =111 Sector allocation according to BSCCASE3 FSA=10 BSC = CMD Command Register F220h R/WAcceptable Operation Two Methods to Clear Interrupt Register in Command Input Write command into INT will automaticallyInterrupt Register System Configuration 1 Register F221h R, R/W Brwl Burst Length BL Information119 Burst Length BLBurst LengthMain Burst LengthSpare RDY Polarity RDYpol Information7 Iobe MRSMode Register Setting Description Write Mode WMWrite Mode Information1 Definition Description Bwps PIL System Configuration 2 Register F222hController Status Register F240h R Otpl Otpbl Otpl Interrupt Status Register F241h R/W INTRsti Read Interrupt RI WI Interrupt Status Conditions Default State ValidEI Interrupt Status Conditions Default State Valid RI Interrupt Status Conditions Nand Flash Write Protection Status Register F24Eh R Start Block Address Register F24Ch R/WStart Block Address Register F24Dh R/W SBA ECC Status Register 4 FF03h R FF03h, default = 0000h ECC Status Register 2 FF01h R FF01h, default = 0000hECC Status Register 3 FF02h R FF02h, default = 0000h ECC Status Register 1 FF00h R Command Based Operation Reset Flex-MuxOneNAND Add BP1 Data 00F0hAdd Data 00E0h 0000h3 Read Identification Data XXXXh4 0090h Read Identification Data Command Reset Flex-MuxOneNAND CommandLoad Data Into Buffer Command Identification Data Description Address Data Out Device Bus Operation Operation ADQ0~15CLK AVD Reset Mode Operation BP-F0h Hot Reset Mode Operation Cold Reset Mode OperationWarm Reset Mode Operation Nand Flash Core Reset Mode Operation Nand Flash Array Write Protection Operation BootRAM Write Protection OperationWrite Protection Operation Nand Array Write Protection States Locked Lock Command Sequence Unlocked Unlock Command SequenceUnlocked All Block Unlock Command Sequence Unlocked Nand Array Write Protection State Start block address+Lock-tight block command 002Ch Nand Flash Array Write Protection State DiagramLocked-tight Lock-Tight Command Sequence Locked-tight Nand Array Write Protection State DBS, DFS is for DDP Samsung strongly recommends to follow the above flow chartLock/Unlock/Lock-TightError completed DQ10=0? All Block Unlock Completed Data Protection During Power Down Operation Load Operation Superload Operation LSB Page Recovery Read Asynchronous Read Mode Operation RM=0, WM=0 Synchronous Read Mode Operation RM=1, WM=XRead Operation Continuous Linear Burst Read Operation 2.2 4-, 8-, 16-, 32-Word Linear Burst Read OperationReserved area is not available on Synchronous read Output Disable Mode Operation Programmable Burst Read Latency OperationHandshaking Operation See Timing Diagram 6.6, 6.7 Synchronous WriteRM=1, WM=1 Data register Program OperationAddressing for program operation MLC Block Paired Page Address Information Paired Page Address Flash Memory If program operation results in an error, map out Block including the page in error and copyDBS, DFS is for DDP Target data to another block Program Interleave can work in Auto INT Interrupt register must not be writtenDBS, DFS is for DDP Cache Program Operation Sector0 Sector7 Last PGM? Cache Program Operation Flow DiagramProgram Error Add F101h DQ=DBS Add DataRAM DQ=Data4KB Interleave Cache Program Operation Results in an error If program operationBlock Add F241h DQ=0000h DQ=Data Copy back completed Copy back ErrorCopy-Back Program Operation with Random Data Input Write ‘DFS , FBA’ o f Fla sh Erase Error Erase OperationBlock Erase Operation Add F100h DQ=DFS*, FBA Add F101h DQ=DBS Erase Interleave1 @DDP Flow ChartINT=1Ready Erase Error Add F101h DQ=DBS Add F241h DQ=5=EI Erase Suspend / Erase Resume Operation Erase Suspend During a Block Erase OperationErase Resume Partition Information PI Block SLC Only PI Block Boundary Information setting PI Block Boundary Information setting stepsPI Block Boundary Information setting Flow Chart PI Block Access mode entry PI Block Access mode entry Flow Chart PI Block Erase Operation Flow Chart In PI Block Access Mode PI Block EraseErasing the PI Area Programming the PI Area PI Block Program OperationMemory location in the PI area can be program Locking the PI PI Update Update the PI AreaAdd F241h DQ15=INT PI updated PI Block Load Operation OTP Operation SLC only OTP Block Area Structure 1st Block OTP Area Structure OTP Block Load Operation OTP Exit OTP Block Program Operation Programming the OTP Area Add DP DQ=Data-in OTP Block Program Operation Flow ChartDo Cold/Warm/Hot Nand Flash Core reset OTP Exit OTPL=0? YES OTP Block Lock Operation Locking the OTPOTP Lock Operation Steps Add F241h DQ15=INT Do Cold reset Automatically UpdatedAdd F241h DQ15=INT Write Data into DataRAM3 Add 1st Word 13.4 1st Block OTP Lock Operation Locking the 1st Block OTP1st Block OTP Lock Operation Steps 100 OTP and 1st Block OTP Lock Operation Locking the OTP and 1st Block OTPOTP and 1st Block OTP simultaneous Lock Operation Steps 102 DQ6 DQ5~DQ0 14 DQ6 Toggle BitStatus DQ15~DQ7 Progress Data Loading Don’t Care ECC Operation ECC Bypass Operation Invalid Block Operation Invalid Block Identification Table Operation Invalid Block Replacement Operation Invalid Block Table Creation Flow Chart Start 1st 1th Nth Block Replacement Operation SequenceBlock a 1st Block B 1th Nth 107 Absolute Maximum Ratings Operating ConditionsKFM4GH6Q4M DC Characteristics ParameterTest Conditions Device Capacitance Valid Block CharacteristicsAC Test Conditions DDP QDP 66MHz 83MHz Unit AC Characteristics for Synchronous Burst ReadSee Timing Diagrams 6.1 Parameter Max Min KFKAGH6Q4MTBD AC Characteristics for Asynchronous ReadKFN8GH6Q4M Min Max AC Characteristics for Asynchronous Write AC Characteristics for Burst Write OperationSee Timing Diagrams Parameter Symbol Min Max Unit 200 AC Characteristics for Load/Program/Erase PerformanceAC Characteristics for INT Auto Mode 114 CLK 8-Word Linear Burst Read Mode with Wrap AroundContinuous Linear Burst Read Mode with Wrap Around RDY Low See AC Characteristics Table DQ0 DQ15Asynchronous Read VA Transition Before Asynchronous Read VA Transition After AVD Low Valid WD Asynchronous WriteADQ15-ADQ0 Hi-Z ≈D7 8-Word Linear Burst Write ModeBurst Write Operation followed by Burst Read 118 Start Initial Burst Write Operation 119 Load Operation Timing See AC Characteristics .7 and TableLoad Command Sequence last two cycles Read Data Completed Da+n Superload Operation Timing Program Command Sequence last two cycles Program Operation Timing122 Timing Ongoing Status ADQ15 Interleave Cache Program OperationADQ0~ Ongoing Status INT bit Erase Command Sequence Block Erase Operation Timing125 Cold Reset Timing Warm Reset Timing CE, OE127 Hot Reset Timing Flex-MuxOneNANDADQi Flex-MuxOneNAND Operation or Idle Nand Flash Core reset Nand Flash Core Reset TimingData Protection Timing During Power Down ADQi Status RD Hi-Z RDY130 INT auto mode Write command into Command Register INT will automatically131 General Operation DQ type Methods of Determining Interrupt StatusINT Type Mono INT Type DDP 132 Synchronous Mode Using the INT Pin Asynchronous Mode Using the INT PinINT Pin to a Host General Purpose I/O Polling the Interrupt Register Status Bit 134 INT pol = ‘High’ Default Determining Rp Value DDP, QDP OnlyRpohm Ready INT pol = ‘Low’Vcc or Vccq Vss KFN8GH6Q4M @ Vcc = 1.8V, Ta = 25C , CL = 30pF Boot Sequence Boot SequenceBoot Loaders in Flex-MuxOneNAND Boot Loaders in Flex-MuxOneNAND Description BL1 NBL3BL2 NBL2 Last Block Address First Block Address Partition of Flex-MuxOneNANDMLC Partition +1 ~ n-1 Blocks Data Register DDP and QDP Description DDPDual Die PackageQDPQuad Die Package 4G product KFM4GH6Q4M 8G product KFN8GH6Q4M141 16G product KFKAGH6Q4M 142