System Configuration 1 Register F221h R, R/W | Samsung KFN8GH6Q4M

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)	FLASH MEMORY

2.8.19 System Configuration 1 Register F221h (R, R/W)

This Read/Write register describes the system configuration.

F221h, default =40C0h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R/W

R/W

R

RM

BRWL

BL

ECC

RDY

INT

IOBE

RDY

Reserv

HF

WM

BWPS

pol

pol

Conf

ed

Read Mode (RM)

RM

0

1

Read Mode

Asynchronous read(default)

Synchronous read

Read Mode Information[15]

Item	Definition				Description
RM	Read Mode		Selects between asynchronous read mode and
RM	Read Mode			synchronous read mode
				synchronous read mode

Burst Read Write Latency (BRWL)

		Latency Cycles (Read/Write)
BRWL
BRWL	under 40MHz	40MHz~66MHz			over 66MHz
	(HF=0)	(HF=0)			(HF=1)
000~010		Reserved

011	3(up to 40MHz. min)	3(N/A)			3(N/A)

100 (default)	4	4(min.)			4(N/A)

101	5	5			5(N/A)

110	6	6			6(min.)

111	7	7			7

* Default value of BRWL and HF value is BRWL=4, HF=0.

For host frequency over 66MHz, BRWL should be 6 or 7 while HF is 1.

For host frequency range of 40MHz~66MHz, BRWL should be set to 4~7 while HF is 0. For host frequency under 40MHz, BRWL should be set to 3~7 while HF is 0.

Burst Read Write Latency (BRWL) Information[14:12]

	Item	Definition	Description
	BRWL	Burst Read Latency /	Specifies the access latency in the burst
	BRWL	Burst Write Latency	read / write transfer for the initial access
		Burst Write Latency	read / write transfer for the initial access

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Image 45

Samsung KFN8GH6Q4M, KFKAGH6Q4M, KFM4GH6Q4M warranty System Configuration 1 Register F221h R, R/W, Brwl

Contents

KFM4GH6Q4M KFN8GH6Q4M KFKAGH6Q4M Revision No History Draft Date Initial issueRemark Corrected errata Oct Ordering Information General Overview Device Architecture Product FeaturesDevice Performance System Hardware Definitions Detailed Product Description Pin Configuration 1 4Gb KFM4GH6Q4M / 8Gb KFN8GH6Q4M63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA4Gb TOP VIEW, Balls Facing Down 63ball Fbga OneNAND Chip 2 16Gb Product KFKAGH6Q4M TBD Multiplexed Address/Data bus Pin DescriptionRegister read cycles Interrupt Memory Array Organization Block DiagramInternal Nand Array Memory Organization OTP Sector BlockMLCBlockSLC Boot code Nand Array OTP Block BootRAM 1KB DataRAM0 2KB DataRAM1 2KBExternal BufferRAM Memory Internal Nand Array Memory Block Block Address Size Memory Map0000h 256KB Block Block Address Block160 Block128Block129 Block161 Block240 00F0h Block238 00EEh Block288 0120h Block257 Block256Block289 0121h Block258 Block290 0122h Block259 Block352 0160h Block321 Block320Block353 0161h Block322 Block354 0162h Block323 Block416 Block384Block385 Block417 Block496 01F0h Block494 01EEh Block544 0220h Block513 Block512Block545 0221h Block514 Block546 0222h Block515 Block608 0260h Block577 Block576Block609 0261h Block578 Block610 0262h Block579 Block672 Block640Block641 Block673 Block752 02F0h Block750 02EEh Block800 0320h Block769 Block768Block801 0321h Block770 Block802 0322h Block771 Block864 0360h Block833 Block832Block865 0361h Block834 Block866 0362h Block835 Block928 Block896Block897 Block929 Block1008 03F0h Block1006 03EEh Area Internal Memory Spare Area Assignment256W Byte Division Address Size Usage Description External Memory BufferRAM Address Map BootRAMSpare area BootRAMMain areaExternal Memory Map Detail Information DataRAMMain area Buf Word Byte External Memory Spare Area Assignment 10054h 802Bh 10056h 802Ch 10058h 802Dh 10074h 803Bh 10076h 803Ch 10078h 803Dh4bit ECC parity values 8046h 1008Ch 8047h 1008Eh 10090h BIBad block Information DataS10092h Managed by internal ECC logic 10094h 804Bh 10096h 804Ch 10098h 804Dh Registers Register Address MapAddress Name Host Description Manufacturer ID Register F000h R Device ID DefaultDevice ID Register F001h R Device Identification Version ID Register F002h Data Buffer Size Register F003h RThis register is reserved for future use Boot Buffer Size Register F004h R Amount of Buffers Register F005h RTechnology Register F006h R Start Address1 Register F100h R/W Start Address2 Register F101h R/W11~15 Start Address3~7 Register F102h~F106h Start Buffer Register F200h R/W Start Address8 Register F107h R/W BSC =111 Sector allocation according to BSCCASE1 FSA=00 BSC =Sector allocation according to BSCCASE2 FSA=01 BSC = Sector allocation according to BSCCASE3 FSA=10 BSC = Acceptable Command Register F220h R/WCMD Operation Two Methods to Clear Interrupt Register in Command Input Write command into INT will automaticallyInterrupt Register Brwl System Configuration 1 Register F221h R, R/W Burst LengthMain Burst LengthSpare Burst Length BLBurst Length BL Information119 RDY Polarity RDYpol Information7 Iobe Write Mode Information1 Definition Description Write Mode WMMRSMode Register Setting Description Bwps Controller Status Register F240h R System Configuration 2 Register F222hPIL Otpl Otpbl Otpl Interrupt Status Register F241h R/W INTRsti EI Interrupt Status Conditions Default State Valid WI Interrupt Status Conditions Default State ValidRead Interrupt RI RI Interrupt Status Conditions Start Block Address Register F24Dh R/W Start Block Address Register F24Ch R/WNand Flash Write Protection Status Register F24Eh R SBA ECC Status Register 3 FF02h R FF02h, default = 0000h ECC Status Register 2 FF01h R FF01h, default = 0000hECC Status Register 4 FF03h R FF03h, default = 0000h ECC Status Register 1 FF00h R Command Based Operation Reset Flex-MuxOneNAND Add BP1 Data 00F0hAdd Data 00E0h 0000h3 Read Identification Data XXXXh4 0090h Load Data Into Buffer Command Reset Flex-MuxOneNAND CommandRead Identification Data Command Identification Data Description Address Data Out Device Bus Operation Operation ADQ0~15CLK AVD BP-F0h Reset Mode Operation Warm Reset Mode Operation Cold Reset Mode OperationHot Reset Mode Operation Nand Flash Core Reset Mode Operation Write Protection Operation BootRAM Write Protection OperationNand Flash Array Write Protection Operation Nand Array Write Protection States Unlocked All Block Unlock Command Sequence Unlocked Unlock Command SequenceLocked Lock Command Sequence Unlocked Nand Array Write Protection State Locked-tight Lock-Tight Command Sequence Nand Flash Array Write Protection State DiagramStart block address+Lock-tight block command 002Ch Locked-tight Nand Array Write Protection State Lock/Unlock/Lock-TightError completed Samsung strongly recommends to follow the above flow chartDBS, DFS is for DDP DQ10=0? All Block Unlock Completed Load Operation Data Protection During Power Down Operation Superload Operation LSB Page Recovery Read Asynchronous Read Mode Operation RM=0, WM=0 Synchronous Read Mode Operation RM=1, WM=XRead Operation Continuous Linear Burst Read Operation 2.2 4-, 8-, 16-, 32-Word Linear Burst Read OperationReserved area is not available on Synchronous read Output Disable Mode Operation Programmable Burst Read Latency OperationHandshaking Operation Synchronous WriteRM=1, WM=1 See Timing Diagram 6.6, 6.7 Addressing for program operation Program OperationData register MLC Block Paired Page Address Paired Page Address Information Flash Memory If program operation results in an error, map out Block including the page in error and copyDBS, DFS is for DDP Target data to another block Program Interleave can work in Auto INT Interrupt register must not be writtenDBS, DFS is for DDP Sector0 Sector7 Cache Program Operation Program Error Cache Program Operation Flow DiagramLast PGM? Add F101h DQ=DBS Add DataRAM DQ=Data4KB Interleave Cache Program Operation Results in an error If program operationBlock Copy-Back Program Operation with Random Data Input Copy back completed Copy back ErrorAdd F241h DQ=0000h DQ=Data Write ‘DFS , FBA’ o f Fla sh Erase Error Erase OperationBlock Erase Operation INT=1Ready Erase Error Erase Interleave1 @DDP Flow ChartAdd F100h DQ=DFS*, FBA Add F101h DQ=DBS Add F101h DQ=DBS Add F241h DQ=5=EI Erase Suspend / Erase Resume Operation Erase Suspend During a Block Erase OperationErase Resume Partition Information PI Block SLC Only PI Block Boundary Information setting PI Block Boundary Information setting stepsPI Block Boundary Information setting Flow Chart PI Block Access mode entry Flow Chart PI Block Access mode entry PI Block Erase Operation Flow Chart In PI Block Access Mode PI Block EraseErasing the PI Area Memory location in the PI area can be program PI Block Program OperationProgramming the PI Area Locking the PI PI Update Update the PI AreaAdd F241h DQ15=INT PI updated PI Block Load Operation OTP Operation SLC only 1st Block OTP Area Structure OTP Block Area Structure OTP Exit OTP Block Load Operation Programming the OTP Area OTP Block Program Operation Do Cold/Warm/Hot Nand Flash Core reset OTP Exit OTP Block Program Operation Flow ChartAdd DP DQ=Data-in OTPL=0? YES OTP Block Lock Operation Locking the OTPOTP Lock Operation Steps Add F241h DQ15=INT Do Cold reset Automatically UpdatedAdd F241h DQ15=INT Write Data into DataRAM3 Add 1st Word 13.4 1st Block OTP Lock Operation Locking the 1st Block OTP1st Block OTP Lock Operation Steps 100 OTP and 1st Block OTP Lock Operation Locking the OTP and 1st Block OTPOTP and 1st Block OTP simultaneous Lock Operation Steps 102 Status DQ15~DQ7 14 DQ6 Toggle BitDQ6 DQ5~DQ0 Progress Data Loading Don’t Care ECC Bypass Operation ECC Operation Invalid Block Identification Table Operation Invalid Block Operation Invalid Block Table Creation Flow Chart Start Invalid Block Replacement Operation Block a Block Replacement Operation Sequence1st 1th Nth 1st Block B 1th Nth 107 Absolute Maximum Ratings Operating ConditionsKFM4GH6Q4M DC Characteristics ParameterTest Conditions AC Test Conditions Valid Block CharacteristicsDevice Capacitance DDP QDP See Timing Diagrams 6.1 Parameter AC Characteristics for Synchronous Burst Read66MHz 83MHz Unit Max Min KFN8GH6Q4M AC Characteristics for Asynchronous ReadKFKAGH6Q4MTBD Min Max AC Characteristics for Asynchronous Write AC Characteristics for Burst Write OperationSee Timing Diagrams Parameter Symbol Min Max Unit AC Characteristics for INT Auto Mode AC Characteristics for Load/Program/Erase Performance200 114 Continuous Linear Burst Read Mode with Wrap Around 8-Word Linear Burst Read Mode with Wrap AroundCLK RDY Asynchronous Read VA Transition Before See AC Characteristics Table DQ0 DQ15Low Asynchronous Read VA Transition After AVD Low ADQ15-ADQ0 Asynchronous WriteValid WD Hi-Z Burst Write Operation followed by Burst Read 8-Word Linear Burst Write Mode≈D7 118 119 Start Initial Burst Write Operation Load Command Sequence last two cycles Read Data See AC Characteristics .7 and TableLoad Operation Timing Completed Da+n Superload Operation Timing Program Command Sequence last two cycles Program Operation Timing122 Ongoing Status Timing ADQ0~ Interleave Cache Program OperationADQ15 Ongoing Status INT bit Erase Command Sequence Block Erase Operation Timing125 Cold Reset Timing Warm Reset Timing CE, OE127 Hot Reset Timing Flex-MuxOneNANDADQi Data Protection Timing During Power Down Nand Flash Core Reset TimingFlex-MuxOneNAND Operation or Idle Nand Flash Core reset ADQi Status RD Hi-Z RDY130 INT auto mode Write command into Command Register INT will automatically131 INT Type Mono INT Type DDP Methods of Determining Interrupt StatusGeneral Operation DQ type 132 Synchronous Mode Using the INT Pin Asynchronous Mode Using the INT PinINT Pin to a Host General Purpose I/O 134 Polling the Interrupt Register Status Bit INT pol = ‘High’ Default Determining Rp Value DDP, QDP OnlyRpohm Vcc or Vccq INT pol = ‘Low’Ready Vss KFN8GH6Q4M @ Vcc = 1.8V, Ta = 25C , CL = 30pF Boot Loaders in Flex-MuxOneNAND Boot SequenceBoot Sequence Boot Loaders in Flex-MuxOneNAND Description BL2 NBL3BL1 NBL2 MLC Partition +1 ~ n-1 Blocks Partition of Flex-MuxOneNANDLast Block Address First Block Address Data Register DDP and QDP Description DDPDual Die PackageQDPQuad Die Package 4G product KFM4GH6Q4M 8G product KFN8GH6Q4M141 142 16G product KFKAGH6Q4M