Program Operation Timing, 122 | Samsung KFM4GH6Q4M, KFN8GH6Q4M

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)	FLASH MEMORY

6.11 Program Operation Timing

See AC Characteristics Table 5.7 and Table 5.9

Program Command Sequence (last two cycles)

Read Status Data

	tAVDP	tWEA
AVD
	tAAVDS	tAAVDH
A/DQ0:	AA	PMA	BA	BD	CA	PCD	≈	SA	In	SA	Completed
A/DQ15	AA	PMA	BA	BD	CA	PCD		SA	Progress	SA

							≈
CE					tDS	tDH	≈
CE							tCER
							tCER
OE						tCH	≈
						tCH

		tWPL
WE							≈
WE		tWPH
		tWPH
	tCS	tWC					tPGM1 or tPGM2
CLK	VIL	tWC					≈
	VIL

	tCER
INT
bit							tCEZ				tCEZ
	Hi-Z						tCEZ				tCEZ
RDY	Hi-Z
RDY

NOTE :

1)AA = Address of address register CA = Address of command register PCD = Program Command

PMA = Address of memory to be programmed BA = Address of BufferRAM to write the data BD = Program Data

SA = Address of status register

2)“In progress” and “complete” refer to status register

3)Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

- 122 -

Page 122

Image 122

Samsung KFM4GH6Q4M, KFN8GH6Q4M, KFKAGH6Q4M warranty Program Operation Timing, Program Command Sequence last two cycles, 122

Contents

KFM4GH6Q4M KFN8GH6Q4M KFKAGH6Q4M Remark Initial issueRevision No History Draft Date Corrected errata Oct Ordering Information General Overview Device Performance Product FeaturesDevice Architecture System Hardware Detailed Product Description Definitions 63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA4Gb Pin Configuration1 4Gb KFM4GH6Q4M / 8Gb KFN8GH6Q4M 2 16Gb Product KFKAGH6Q4M TBD TOP VIEW, Balls Facing Down 63ball Fbga OneNAND Chip Register read cycles Pin DescriptionMultiplexed Address/Data bus Interrupt Internal Nand Array Memory Organization Block DiagramMemory Array Organization OTP BlockSLC SectorBlockMLC External BufferRAM Memory BootRAM 1KB DataRAM0 2KB DataRAM1 2KBBoot code Nand Array OTP Block Internal Nand Array Memory 0000h Memory MapBlock Block Address Size 256KB Block Block Address Block129 Block128Block160 Block161 Block238 00EEh Block240 00F0h Block289 0121h Block258 Block256Block288 0120h Block257 Block290 0122h Block259 Block353 0161h Block322 Block320Block352 0160h Block321 Block354 0162h Block323 Block385 Block384Block416 Block417 Block494 01EEh Block496 01F0h Block545 0221h Block514 Block512Block544 0220h Block513 Block546 0222h Block515 Block609 0261h Block578 Block576Block608 0260h Block577 Block610 0262h Block579 Block641 Block640Block672 Block673 Block750 02EEh Block752 02F0h Block801 0321h Block770 Block768Block800 0320h Block769 Block802 0322h Block771 Block865 0361h Block834 Block832Block864 0360h Block833 Block866 0362h Block835 Block897 Block896Block928 Block929 Block1006 03EEh Block1008 03F0h 256W Internal Memory Spare Area AssignmentArea Byte External Memory BufferRAM Address Map Division Address Size Usage Description External Memory Map Detail Information BootRAMMain areaBootRAMSpare area DataRAMMain area External Memory Spare Area Assignment Buf Word Byte 4bit ECC parity values 8046h 1008Ch 8047h 1008Eh 10054h 802Bh 10056h 802Ch 10058h 802Dh10074h 803Bh 10076h 803Ch 10078h 803Dh 10092h Managed by internal ECC logic DataS10090h BIBad block Information 10094h 804Bh 10096h 804Ch 10098h 804Dh Address Name Host Description RegistersRegister Address Map Device ID Register F001h R Device ID DefaultManufacturer ID Register F000h R Device Identification This register is reserved for future use Version ID Register F002hData Buffer Size Register F003h R Technology Register F006h R Boot Buffer Size Register F004h RAmount of Buffers Register F005h R 11~15 Start Address3~7 Register F102h~F106h Start Address1 Register F100h R/WStart Address2 Register F101h R/W Start Address8 Register F107h R/W Start Buffer Register F200h R/W Sector allocation according to BSCCASE2 FSA=01 BSC = Sector allocation according to BSCCASE1 FSA=00 BSC =BSC =111 Sector allocation according to BSCCASE3 FSA=10 BSC = CMD Command Register F220h R/WAcceptable Operation Interrupt Register Two Methods to Clear Interrupt Register in Command InputWrite command into INT will automatically System Configuration 1 Register F221h R, R/W Brwl Burst Length BL Information119 Burst Length BLBurst LengthMain Burst LengthSpare RDY Polarity RDYpol Information7 Iobe MRSMode Register Setting Description Write Mode WMWrite Mode Information1 Definition Description Bwps PIL System Configuration 2 Register F222hController Status Register F240h R Otpl Otpbl Otpl Rsti Interrupt Status Register F241h R/WINT Read Interrupt RI WI Interrupt Status Conditions Default State ValidEI Interrupt Status Conditions Default State Valid RI Interrupt Status Conditions Nand Flash Write Protection Status Register F24Eh R Start Block Address Register F24Ch R/WStart Block Address Register F24Dh R/W SBA ECC Status Register 4 FF03h R FF03h, default = 0000h ECC Status Register 2 FF01h R FF01h, default = 0000hECC Status Register 3 FF02h R FF02h, default = 0000h ECC Status Register 1 FF00h R Add Data 00E0h 0000h3 Read Identification Data XXXXh4 0090h Command Based OperationReset Flex-MuxOneNAND Add BP1 Data 00F0h Read Identification Data Command Reset Flex-MuxOneNAND CommandLoad Data Into Buffer Command Identification Data Description Address Data Out CLK AVD Device Bus OperationOperation ADQ0~15 Reset Mode Operation BP-F0h Hot Reset Mode Operation Cold Reset Mode OperationWarm Reset Mode Operation Nand Flash Core Reset Mode Operation Nand Flash Array Write Protection Operation BootRAM Write Protection OperationWrite Protection Operation Nand Array Write Protection States Locked Lock Command Sequence Unlocked Unlock Command SequenceUnlocked All Block Unlock Command Sequence Unlocked Nand Array Write Protection State Start block address+Lock-tight block command 002Ch Nand Flash Array Write Protection State DiagramLocked-tight Lock-Tight Command Sequence Locked-tight Nand Array Write Protection State DBS, DFS is for DDP Samsung strongly recommends to follow the above flow chartLock/Unlock/Lock-TightError completed DQ10=0? All Block Unlock Completed Data Protection During Power Down Operation Load Operation Superload Operation LSB Page Recovery Read Read Operation Asynchronous Read Mode Operation RM=0, WM=0Synchronous Read Mode Operation RM=1, WM=X Reserved area is not available on Synchronous read Continuous Linear Burst Read Operation2.2 4-, 8-, 16-, 32-Word Linear Burst Read Operation Handshaking Operation Output Disable Mode OperationProgrammable Burst Read Latency Operation See Timing Diagram 6.6, 6.7 Synchronous WriteRM=1, WM=1 Data register Program OperationAddressing for program operation MLC Block Paired Page Address Information Paired Page Address Flash Memory DBS, DFS is for DDP Target data to another block If program operation results in an error, map outBlock including the page in error and copy DBS, DFS is for DDP Program Interleave can work in Auto INTInterrupt register must not be written Cache Program Operation Sector0 Sector7 Last PGM? Cache Program Operation Flow DiagramProgram Error Add F101h DQ=DBS Add DataRAM DQ=Data4KB Interleave Cache Program Operation Block Results in an errorIf program operation Add F241h DQ=0000h DQ=Data Copy back completed Copy back ErrorCopy-Back Program Operation with Random Data Input Write ‘DFS , FBA’ o f Fla sh Block Erase Operation Erase ErrorErase Operation Add F100h DQ=DFS*, FBA Add F101h DQ=DBS Erase Interleave1 @DDP Flow ChartINT=1Ready Erase Error Add F101h DQ=DBS Add F241h DQ=5=EI Erase Resume Erase Suspend / Erase Resume OperationErase Suspend During a Block Erase Operation Partition Information PI Block SLC Only PI Block Boundary Information setting Flow Chart PI Block Boundary Information settingPI Block Boundary Information setting steps PI Block Access mode entry PI Block Access mode entry Flow Chart Erasing the PI Area PI Block Erase Operation Flow Chart In PI Block Access ModePI Block Erase Programming the PI Area PI Block Program OperationMemory location in the PI area can be program Locking the PI Add F241h DQ15=INT PI updated PI UpdateUpdate the PI Area PI Block Load Operation OTP Operation SLC only OTP Block Area Structure 1st Block OTP Area Structure OTP Block Load Operation OTP Exit OTP Block Program Operation Programming the OTP Area Add DP DQ=Data-in OTP Block Program Operation Flow ChartDo Cold/Warm/Hot Nand Flash Core reset OTP Exit OTPL=0? YES OTP Lock Operation Steps OTP Block Lock OperationLocking the OTP Add F241h DQ15=INT Write Data into DataRAM3 Add 1st Word Add F241h DQ15=INT Do Cold resetAutomatically Updated 1st Block OTP Lock Operation Steps 13.4 1st Block OTP Lock OperationLocking the 1st Block OTP 100 OTP and 1st Block OTP simultaneous Lock Operation Steps OTP and 1st Block OTP Lock OperationLocking the OTP and 1st Block OTP 102 DQ6 DQ5~DQ0 14 DQ6 Toggle BitStatus DQ15~DQ7 Progress Data Loading Don’t Care ECC Operation ECC Bypass Operation Invalid Block Operation Invalid Block Identification Table Operation Invalid Block Replacement Operation Invalid Block Table Creation Flow Chart Start 1st 1th Nth Block Replacement Operation SequenceBlock a 1st Block B 1th Nth 107 KFM4GH6Q4M Absolute Maximum RatingsOperating Conditions Test Conditions DC CharacteristicsParameter Device Capacitance Valid Block CharacteristicsAC Test Conditions DDP QDP 66MHz 83MHz Unit AC Characteristics for Synchronous Burst ReadSee Timing Diagrams 6.1 Parameter Max Min KFKAGH6Q4MTBD AC Characteristics for Asynchronous ReadKFN8GH6Q4M Min Max See Timing Diagrams Parameter Symbol Min Max Unit AC Characteristics for Asynchronous WriteAC Characteristics for Burst Write Operation 200 AC Characteristics for Load/Program/Erase PerformanceAC Characteristics for INT Auto Mode 114 CLK 8-Word Linear Burst Read Mode with Wrap AroundContinuous Linear Burst Read Mode with Wrap Around RDY Low See AC Characteristics Table DQ0 DQ15Asynchronous Read VA Transition Before Asynchronous Read VA Transition After AVD Low Valid WD Asynchronous WriteADQ15-ADQ0 Hi-Z ≈D7 8-Word Linear Burst Write ModeBurst Write Operation followed by Burst Read 118 Start Initial Burst Write Operation 119 Load Operation Timing See AC Characteristics .7 and TableLoad Command Sequence last two cycles Read Data Completed Da+n Superload Operation Timing 122 Program Command Sequence last two cyclesProgram Operation Timing Timing Ongoing Status ADQ15 Interleave Cache Program OperationADQ0~ Ongoing Status INT bit 125 Erase Command SequenceBlock Erase Operation Timing Cold Reset Timing 127 Warm Reset TimingCE, OE ADQi Hot Reset TimingFlex-MuxOneNAND Flex-MuxOneNAND Operation or Idle Nand Flash Core reset Nand Flash Core Reset TimingData Protection Timing During Power Down ADQi 130 Status RD Hi-ZRDY 131 INT auto modeWrite command into Command Register INT will automatically General Operation DQ type Methods of Determining Interrupt StatusINT Type Mono INT Type DDP 132 INT Pin to a Host General Purpose I/O Synchronous Mode Using the INT PinAsynchronous Mode Using the INT Pin Polling the Interrupt Register Status Bit 134 Rpohm INT pol = ‘High’ DefaultDetermining Rp Value DDP, QDP Only Ready INT pol = ‘Low’Vcc or Vccq Vss KFN8GH6Q4M @ Vcc = 1.8V, Ta = 25C , CL = 30pF Boot Sequence Boot SequenceBoot Loaders in Flex-MuxOneNAND Boot Loaders in Flex-MuxOneNAND Description BL1 NBL3BL2 NBL2 Last Block Address First Block Address Partition of Flex-MuxOneNANDMLC Partition +1 ~ n-1 Blocks Data Register QDPQuad Die Package DDP and QDP DescriptionDDPDual Die Package 141 4G product KFM4GH6Q4M8G product KFN8GH6Q4M 16G product KFKAGH6Q4M 142

Samsung KFM4GH6Q4M Program Operation Timing, Program Command Sequence last two cycles, 122

Models: KFN8GH6Q4M KFM4GH6Q4M KFKAGH6Q4M

FLASH MEMORY

6.11 Program Operation Timing

See AC Characteristics Table 5.7 and Table 5.9

Program Command Sequence (last two cycles)

CLK

INT

RDY

- 122 -