Iobe | Samsung KFM4GH6Q4M, KFN8GH6Q4M, KFKAGH6Q4M specification

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)	FLASH MEMORY

I/O Buffer Enable (IOBE)

IOBE is the I/O Buffer Enable for the INT and RDY signals. At startup, INT and RDY outputs are High-Z. Bits 6 and 7 become valid after IOBE is set to "1". IOBE can be reset by a Cold Reset or by writing "0" to bit 5 of System Configuration1 Register.

I/O Buffer Enable Information[5]

Item	Definition	Description
IOBE	I/O Buffer Enable for INT and	0 = disable (default)
IOBE	RDY signals	1 = enable
	RDY signals	1 = enable

RDY Configuration (RDY conf)
RDY Configuration Information[4]

Item	Definition	Description
RDY conf	RDY configuration	0=active with valid data (default)
RDY conf	RDY configuration	1=active one clock before valid data
		1=active one clock before valid data

HF Enable (HF)

Description

HF Disable (default, under 66MHz)

HF Enable (over 66MHz)

HF Information[2]

Item	Definition	Description
HF	High Frequency	Selects between HF Disable and
HF	High Frequency	HF Enable
		HF Enable

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Samsung KFM4GH6Q4M, KFN8GH6Q4M, KFKAGH6Q4M warranty Iobe

Contents

KFM4GH6Q4M KFN8GH6Q4M KFKAGH6Q4M Corrected errata Initial issueRevision No History Draft Date Remark Oct Ordering Information General Overview System Hardware Product FeaturesDevice Architecture Device Performance Definitions Detailed Product Description 63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA4Gb Pin Configuration1 4Gb KFM4GH6Q4M / 8Gb KFN8GH6Q4M TOP VIEW, Balls Facing Down 63ball Fbga OneNAND Chip 2 16Gb Product KFKAGH6Q4M TBD Interrupt Pin DescriptionMultiplexed Address/Data bus Register read cycles OTP Block DiagramMemory Array Organization Internal Nand Array Memory Organization BlockSLC SectorBlockMLC Internal Nand Array Memory BootRAM 1KB DataRAM0 2KB DataRAM1 2KBBoot code Nand Array OTP Block External BufferRAM Memory 256KB Memory MapBlock Block Address Size 0000h Block Block Address Block161 Block128Block160 Block129 Block240 00F0h Block238 00EEh Block290 0122h Block259 Block256Block288 0120h Block257 Block289 0121h Block258 Block354 0162h Block323 Block320Block352 0160h Block321 Block353 0161h Block322 Block417 Block384Block416 Block385 Block496 01F0h Block494 01EEh Block546 0222h Block515 Block512Block544 0220h Block513 Block545 0221h Block514 Block610 0262h Block579 Block576Block608 0260h Block577 Block609 0261h Block578 Block673 Block640Block672 Block641 Block752 02F0h Block750 02EEh Block802 0322h Block771 Block768Block800 0320h Block769 Block801 0321h Block770 Block866 0362h Block835 Block832Block864 0360h Block833 Block865 0361h Block834 Block929 Block896Block928 Block897 Block1008 03F0h Block1006 03EEh Byte Internal Memory Spare Area AssignmentArea 256W Division Address Size Usage Description External Memory BufferRAM Address Map DataRAMMain area BootRAMMain areaBootRAMSpare area External Memory Map Detail Information Buf Word Byte External Memory Spare Area Assignment 4bit ECC parity values 8046h 1008Ch 8047h 1008Eh 10054h 802Bh 10056h 802Ch 10058h 802Dh10074h 803Bh 10076h 803Ch 10078h 803Dh 10094h 804Bh 10096h 804Ch 10098h 804Dh DataS10090h BIBad block Information 10092h Managed by internal ECC logic Address Name Host Description RegistersRegister Address Map Device Identification Device ID DefaultManufacturer ID Register F000h R Device ID Register F001h R This register is reserved for future use Version ID Register F002hData Buffer Size Register F003h R Technology Register F006h R Boot Buffer Size Register F004h RAmount of Buffers Register F005h R 11~15 Start Address3~7 Register F102h~F106h Start Address1 Register F100h R/WStart Address2 Register F101h R/W Start Buffer Register F200h R/W Start Address8 Register F107h R/W Sector allocation according to BSCCASE3 FSA=10 BSC = Sector allocation according to BSCCASE1 FSA=00 BSC =BSC =111 Sector allocation according to BSCCASE2 FSA=01 BSC = Operation Command Register F220h R/WAcceptable CMD Interrupt Register Two Methods to Clear Interrupt Register in Command InputWrite command into INT will automatically Brwl System Configuration 1 Register F221h R, R/W RDY Polarity RDYpol Information7 Burst Length BLBurst LengthMain Burst LengthSpare Burst Length BL Information119 Iobe Bwps Write Mode WMWrite Mode Information1 Definition Description MRSMode Register Setting Description Otpl Otpbl System Configuration 2 Register F222hController Status Register F240h R PIL Otpl Rsti Interrupt Status Register F241h R/WINT RI Interrupt Status Conditions WI Interrupt Status Conditions Default State ValidEI Interrupt Status Conditions Default State Valid Read Interrupt RI SBA Start Block Address Register F24Ch R/WStart Block Address Register F24Dh R/W Nand Flash Write Protection Status Register F24Eh R ECC Status Register 1 FF00h R ECC Status Register 2 FF01h R FF01h, default = 0000hECC Status Register 3 FF02h R FF02h, default = 0000h ECC Status Register 4 FF03h R FF03h, default = 0000h Add Data 00E0h 0000h3 Read Identification Data XXXXh4 0090h Command Based OperationReset Flex-MuxOneNAND Add BP1 Data 00F0h Identification Data Description Address Data Out Reset Flex-MuxOneNAND CommandLoad Data Into Buffer Command Read Identification Data Command CLK AVD Device Bus OperationOperation ADQ0~15 BP-F0h Reset Mode Operation Nand Flash Core Reset Mode Operation Cold Reset Mode OperationWarm Reset Mode Operation Hot Reset Mode Operation Nand Array Write Protection States BootRAM Write Protection OperationWrite Protection Operation Nand Flash Array Write Protection Operation Unlocked Nand Array Write Protection State Unlocked Unlock Command SequenceUnlocked All Block Unlock Command Sequence Locked Lock Command Sequence Locked-tight Nand Array Write Protection State Nand Flash Array Write Protection State DiagramLocked-tight Lock-Tight Command Sequence Start block address+Lock-tight block command 002Ch DQ10=0? Samsung strongly recommends to follow the above flow chartLock/Unlock/Lock-TightError completed DBS, DFS is for DDP All Block Unlock Completed Load Operation Data Protection During Power Down Operation Superload Operation LSB Page Recovery Read Read Operation Asynchronous Read Mode Operation RM=0, WM=0Synchronous Read Mode Operation RM=1, WM=X Reserved area is not available on Synchronous read Continuous Linear Burst Read Operation2.2 4-, 8-, 16-, 32-Word Linear Burst Read Operation Handshaking Operation Output Disable Mode OperationProgrammable Burst Read Latency Operation Synchronous WriteRM=1, WM=1 See Timing Diagram 6.6, 6.7 MLC Block Program OperationAddressing for program operation Data register Paired Page Address Paired Page Address Information Flash Memory DBS, DFS is for DDP Target data to another block If program operation results in an error, map outBlock including the page in error and copy DBS, DFS is for DDP Program Interleave can work in Auto INTInterrupt register must not be written Sector0 Sector7 Cache Program Operation Add F101h DQ=DBS Add DataRAM DQ=Data4KB Cache Program Operation Flow DiagramProgram Error Last PGM? Interleave Cache Program Operation Block Results in an errorIf program operation Write ‘DFS , FBA’ o f Fla sh Copy back completed Copy back ErrorCopy-Back Program Operation with Random Data Input Add F241h DQ=0000h DQ=Data Block Erase Operation Erase ErrorErase Operation Add F101h DQ=DBS Add F241h DQ=5=EI Erase Interleave1 @DDP Flow ChartINT=1Ready Erase Error Add F100h DQ=DFS*, FBA Add F101h DQ=DBS Erase Resume Erase Suspend / Erase Resume OperationErase Suspend During a Block Erase Operation Partition Information PI Block SLC Only PI Block Boundary Information setting Flow Chart PI Block Boundary Information settingPI Block Boundary Information setting steps PI Block Access mode entry Flow Chart PI Block Access mode entry Erasing the PI Area PI Block Erase Operation Flow Chart In PI Block Access ModePI Block Erase Locking the PI PI Block Program OperationMemory location in the PI area can be program Programming the PI Area Add F241h DQ15=INT PI updated PI UpdateUpdate the PI Area PI Block Load Operation OTP Operation SLC only 1st Block OTP Area Structure OTP Block Area Structure OTP Exit OTP Block Load Operation Programming the OTP Area OTP Block Program Operation OTPL=0? YES OTP Block Program Operation Flow ChartDo Cold/Warm/Hot Nand Flash Core reset OTP Exit Add DP DQ=Data-in OTP Lock Operation Steps OTP Block Lock OperationLocking the OTP Add F241h DQ15=INT Write Data into DataRAM3 Add 1st Word Add F241h DQ15=INT Do Cold resetAutomatically Updated 1st Block OTP Lock Operation Steps 13.4 1st Block OTP Lock OperationLocking the 1st Block OTP 100 OTP and 1st Block OTP simultaneous Lock Operation Steps OTP and 1st Block OTP Lock OperationLocking the OTP and 1st Block OTP 102 Progress Data Loading Don’t Care 14 DQ6 Toggle BitStatus DQ15~DQ7 DQ6 DQ5~DQ0 ECC Bypass Operation ECC Operation Invalid Block Identification Table Operation Invalid Block Operation Invalid Block Table Creation Flow Chart Start Invalid Block Replacement Operation 1st Block B 1th Nth 107 Block Replacement Operation SequenceBlock a 1st 1th Nth KFM4GH6Q4M Absolute Maximum RatingsOperating Conditions Test Conditions DC CharacteristicsParameter DDP QDP Valid Block CharacteristicsAC Test Conditions Device Capacitance Max Min AC Characteristics for Synchronous Burst ReadSee Timing Diagrams 6.1 Parameter 66MHz 83MHz Unit Min Max AC Characteristics for Asynchronous ReadKFN8GH6Q4M KFKAGH6Q4MTBD See Timing Diagrams Parameter Symbol Min Max Unit AC Characteristics for Asynchronous WriteAC Characteristics for Burst Write Operation 114 AC Characteristics for Load/Program/Erase PerformanceAC Characteristics for INT Auto Mode 200 RDY 8-Word Linear Burst Read Mode with Wrap AroundContinuous Linear Burst Read Mode with Wrap Around CLK Asynchronous Read VA Transition After AVD Low See AC Characteristics Table DQ0 DQ15Asynchronous Read VA Transition Before Low Hi-Z Asynchronous WriteADQ15-ADQ0 Valid WD 118 8-Word Linear Burst Write ModeBurst Write Operation followed by Burst Read ≈D7 119 Start Initial Burst Write Operation Completed Da+n See AC Characteristics .7 and TableLoad Command Sequence last two cycles Read Data Load Operation Timing Superload Operation Timing 122 Program Command Sequence last two cyclesProgram Operation Timing Ongoing Status Timing Ongoing Status INT bit Interleave Cache Program OperationADQ0~ ADQ15 125 Erase Command SequenceBlock Erase Operation Timing Cold Reset Timing 127 Warm Reset TimingCE, OE ADQi Hot Reset TimingFlex-MuxOneNAND ADQi Nand Flash Core Reset TimingData Protection Timing During Power Down Flex-MuxOneNAND Operation or Idle Nand Flash Core reset 130 Status RD Hi-ZRDY 131 INT auto modeWrite command into Command Register INT will automatically 132 Methods of Determining Interrupt StatusINT Type Mono INT Type DDP General Operation DQ type INT Pin to a Host General Purpose I/O Synchronous Mode Using the INT PinAsynchronous Mode Using the INT Pin 134 Polling the Interrupt Register Status Bit Rpohm INT pol = ‘High’ DefaultDetermining Rp Value DDP, QDP Only Vss KFN8GH6Q4M @ Vcc = 1.8V, Ta = 25C , CL = 30pF INT pol = ‘Low’Vcc or Vccq Ready Boot Loaders in Flex-MuxOneNAND Description Boot SequenceBoot Loaders in Flex-MuxOneNAND Boot Sequence NBL2 NBL3BL2 BL1 Data Register Partition of Flex-MuxOneNANDMLC Partition +1 ~ n-1 Blocks Last Block Address First Block Address QDPQuad Die Package DDP and QDP DescriptionDDPDual Die Package 141 4G product KFM4GH6Q4M8G product KFN8GH6Q4M 142 16G product KFKAGH6Q4M