Samsung KFKAGH6Q4M, KFN8GH6Q4M, KFM4GH6Q4M warranty Interleave Cache Program Operation

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)	FLASH MEMORY

3.9.2 Interleave Cache Program Operation

The Interleave Cache Program is available only on DDP. Host can write data on a chip while programming another chip with this operation.

Interleave Cache Program is executing as following:

1.4KB Data are written from host to DataRAMs in Chip1.

2.Cache Program command issue. This will turn INT bit to busy state1), OnGo bit sets to ‘1’.

(Note that before issuing ‘Interleave Cache Program Command’, host should make sure that the target blocks are unlocked.)

3.4KB data will be sequentially transferred to each page buffer in NAND Flash Array.

4.While these data are transferring, Host can write another 4KB Data to DataRAM in Chip2.

5.When the transfer operation is completed, programming into NAND Flash Array will automatically start, and at the same time, INT bit will turn to ‘1’ to indicate that DataRAMs are now ready to be written with next 4KB data.

6.Second 4KB is writable on Chip1 when INT1 goes to ‘1’.

7.When second 4KB is written to two DataRAMs of Chip1, another Cache Program command is issued and INT1 bit will go to ‘0’1) again.

When INT bit goes to ‘1’ after second data transfer from DataRAMs to Page Buffers are complete, user may check the Status Register to check the Cache program status. During Cache Program, previous bit shows the status of previous program operation.

For the final 4KB program of Interleave Cache Program scheme, host should issue Program Command(0080h) on each chip. If host issues 0080h on only a chip, another chip will be on operation as it is not finished. Ongo status bit will show the ongoing status of each chip. Its oper- ation is same as Cache Program operation on each chip. Error bit will show the pass/fail status of each chip of Interleave Cache program, and previous ~ current bit will show where the error occurred accordingly .

Note that OTP block and 1st block OTP cannot be Interleave Cache Programmed.

Interleave Cache Program operation must be utilized within a same area partitioned as SLC or MLC.

Page A	Sector0	Sector7	DataRAM0
			Page Buffer
		3’) Program
			(4 KB)
Page B			DataRAM1
			2’) Copy to
			Page Buffer
			4 KB

Page A	Sector0	Sector7	DataRAM0
			Page Buffer
		4’) Program
			(4 KB)
Page B			DataRAM1
			3’’) Copy to
			Page Buffer
			4 KB

1)Data Write, Issue Program Command (Page A)

3)Check for INT bit = 1, then Data write (Page B)

2)Data Write, Issue Program Command (Page A)

4)Check for INT bit = 1, then Data write (Page B)

NOTE :

2 and 2’ are concurrent; 3, 3’ and 3’’ are concurrent; 4 and 4’ are concurrent.

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