Samsung KFM4GH6Q4M, KFN8GH6Q4M, KFKAGH6Q4M warranty AC Characteristics for Asynchronous Write

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)	FLASH MEMORY

5.7 AC Characteristics for Asynchronous Write

See Timing Diagrams 6.5

					Parameter	Symbol	Min	Max	Unit
		Cycle Time				tWC	70	-	ns
WE
			low pulse width			tAVDP	12	-	ns
AVD
Address Setup Time						tAAVDS	5	-	ns
Address Hold Time						tAAVDH	6	-	ns
Data Setup Time						tDS	30	-	ns
Data Hold Time						tDH	0	-	ns
	Setup Time					tCS	0	-	ns
CE
	Hold Time					tCH	0	-	ns
CE
		Pulse Width				tWPL	40	-	ns
WE
		Pulse Width High				tWPH	30	-	ns
WE
		Disable to			Enable	tWEA	15	-	ns
WE				AVD
	Low to RDY Valid					tCER	-	15	ns
CE
	Disable to Output & RDY High Z					tCEZ	-	20	ns
CE

5.8 AC Characteristics for Burst Write Operation

See Timing Diagrams 6.6, 6.7 and 6.8.

					Parameter	Symbol		66MHz			83MHz		Unit
							Min		Max	Min		Max
Clock						CLK1)	1		66	1		83	MHz
Clock Cycle						tCLK	15		-	12		-	ns
			Setup to CLK			tAVDS	5		-	4		-	ns
AVD
			Hold Time from CLK			tAVDH	2		-	2		-	ns
AVD
Address Setup Time to CLK						tACS	5		-	4		-	ns
Address Hold Time from CLK						tACH	6		-	6		-	ns
Data Setup Time to CLK						tWDS	5		-	4		-	ns
Data Hold Time from CLK						tWDH	2		-	2		-	ns
		Setup Time to CLK				tWES	5		-	4		-	ns
WE
		Hold Time from CLK				tWEH	6		-	6		-	ns
WE
CLK High or Low Time						tCLKH/L	tCLK/3		-	5		-	ns
	high pulse width					tCEHP	10		-	10		-	ns
CE
CLK to RDY Valid						tRDYO	-		11	-		9	ns
CLK to RDY Setup Time						tRDYA	-		11	-		9	ns
RDY Setup Time to CLK						tRDYS	4		-	3		-	ns
	low to RDY valid					tCER	-		15	-		15	ns
CE
Clock to					disable	tCEH	2		tCLK-4.5	2		tCLK-4.5	ns
				CE
	Setup Time to CLK					tCES	6		-	4.5		-	ns
CE
	Disable to Output & RDY High Z					tCEZ	-		20	-		20	ns
CE

NOTE :

1)Target Clock frequency is 83Mhz

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