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Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
KFM4GH6Q4M KFN8GH6Q4M KFKAGH6Q4M
4Gb Flex-MuxOneNAND M-die
Revision History
Document Title
Flex-MuxOneNAND
Revision History
Revision No.
Revision History
Revision No.
History
Draft Date
Remark
1.0 INTRODUCTION
K F x x H 6 Q 4 M - D E x x
1.2 General Overview
Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
1.3 Product Features
2.0 DEVICE DESCRIPTION
2.1 Detailed Product Description
2.2 Definitions
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
2.3 Pin Configuration
2.3.1 4Gb (KFM4GH6Q4M) / 8Gb (KFN8GH6Q4M)
2.3.2 16Gb Product (KFKAGH6Q4M) (TBD)
2.4 Pin Description
ADQ15~ADQ0 I/O
Interrupt
2.5 Block Diagram
2.6 Memory Array Organization
2.6.1 Internal (NAND Array) Memory Organization
Sector
Block(MLC)
Page
Block(SLC)
2.6.2 External (BufferRAM) Memory Organization
{
Nand Array
{
Host
OTP Block
2.7 Memory Map
2.7.1 Internal (NAND Array) Memory Organization
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Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
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2.7.2 Internal Memory Spare Area Assignment
2.7.3 External Memory (BufferRAM) Address Map
2.7.4 External Memory Map Detail Information
2.7.5 External Memory Spare Area Assignment
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2.8 Registers
2.8.1 Register Address Map
2.8.2 Manufacturer ID Register F000h (R)
2.8.3 Device ID Register F001h (R)
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2.8.6 Boot Buffer Size Register F004h (R)
2.8.7 Amount of Buffers Register F005h (R)
2.8.8 Technology Register F006h (R)
2.8.9 Start Address1 Register F100h (R/W)
2.8.10 Start Address2 Register F101h (R/W)
2.8.11~15 Start Address3~7 Register F102h~F106h
2.8.16 Start Address8 Register F107h (R/W)
2.8.17 Start Buffer Register F200h (R/W)
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2.8.18 Command Register F220h (R/W)
2.8.18.1 Two Methods to Clear Interrupt Register in Command Input
2.8.19 System Configuration 1 Register F221h (R, R/W)
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2.8.20 System Configuration 2 Register F222h
2.8.21 Controller Status Register F240h (R)
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2.8.22 Interrupt Status Register F241h (R/W)
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2.8.23 Start Block Address Register F24Ch (R/W)
2.8.24 Start Block Address Register F24Dh (R/W)
2.8.25 NAND Flash Write Protection Status Register F24Eh (R)
2.8.26 ECC Status Register 1 FF00h (R)
2.8.27 ECC Status Register 2 FF01h (R)
2.8.28 ECC Status Register 3 FF02h (R)
2.8.29 ECC Status Register 4 FF03h (R)
3.0 DEVICE OPERATION
3.1 Command Based Operation
3.1.1 Reset Flex-MuxOneNAND Command
3.1.2 Load Data Into Buffer Command
3.1.3 Read Identification Data Command
3.2 Device Bus Operation
3.3 Reset Mode Operation
3.3.1 Cold Reset Mode Operation
3.3.2 Warm Reset Mode Operation
3.3.3 Hot Reset Mode Operation
3.3.4 NAND Flash Core Reset Mode Operation
3.4 Write Protection Operation
3.4.1 BootRAM Write Protection Operation
3.4.2 NAND Flash Array Write Protection Operation
3.4.3 NAND Array Write Protection States
3.4.3.1 Unlocked NAND Array Write Protection State
3.4.3.2 Locked NAND Array Write Protection State
3.4.3.3 Locked-tight NAND Array Write Protection State
3.4.4 NAND Flash Array Write Protection State Diagram
* Samsung strongly recommends to follow the above flow chart
*Samsung strongly recommends to follow the above flow chart
3.5 Data Protection During Power Down Operation
3.6 Load Operation
3.6.1 Superload Operation
3.6.2 LSB Page Recovery Read
3.7 Read Operation
3.7.1 Asynchronous Read Mode Operation (RM=0, WM=0)
3.7.2 Synchronous Read Mode Operation (RM=1, WM=X)
3.7.2.1 Continuous Linear Burst Read Operation
3.7.2.2 4-, 8-, 16-, 32-Word Linear Burst Read Operation
3.7.2.3 Programmable Burst Read Latency Operation
3.7.3 Handshaking Operation
3.7.4 Output Disable Mode Operation
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3.9 Program Operation
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. . .
target data to another block.
Program Interleave(@DDP) Flow Chart
{
}
3*
*
3.9.1 Cache Program Operation
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3.9.2 Interleave Cache Program Operation
*
3.10 Copy-Back Program Operation with Random Data Input
3.11 Erase Operation
3.11.1 Block Erase Operation
{
}
*
{
3.11.2 Erase Suspend / Erase Resume Operation
3.12 Partition Information (PI) Block (SLC Only)
SLC area (Default) SLC area
[NAND Flash Array]
MLC area
3.12.1 PI Block Boundary Information setting
Start
3.12.1.1 PI Block Access mode entry
* DBS, DFS is for DDP
3.12.1.2 PI Block Erase
* DBS, DFS is for DDP
3.12.1.3 PI Block Program Operation
3.12.1.4 PI Update
3.12.2 PI Block Load Operation
}
Add: F220h
3.13 OTP Operation (SLC only)
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3.13.1 OTP Block Load Operation
Add: F220h
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3.13.3 OTP Block Lock Operation
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3.13.4 1st Block OTP Lock Operation
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3.13.5 OTP and 1st Block OTP Lock Operation
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3.15 ECC Operation
3.15.1 ECC Bypass Operation
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3.16.2 Invalid Block Replacement Operation
{
{
4.0 DC CHARACTERISTICS
4.1 Absolute Maximum Ratings
4.2 Operating Conditions
4.3 DC Characteristics
5.0 AC CHARACTERISTICS
5.1 AC Test Conditions
5.2 Device Capacitance
CAPACITANCE
5.3 Valid Block Characteristics
5.4 AC Characteristics for Synchronous Burst Read
5.5 AC Characteristics for Asynchronous Read
5.6 AC Characteristics for Warm Reset (RP), Hot Reset and NAND Flash Core Reset
5.7 AC Characteristics for Asynchronous Write
5.8 AC Characteristics for Burst Write Operation
5.9 AC Characteristics for Load/Program/Erase Performance
5.10 AC Characteristics for INT Auto Mode
6.0 TIMING DIAGRAMS
6.1 8-Word Linear Burst Read Mode with Wrap Around
6.2 Continuous Linear Burst Read Mode with Wrap Around
6.3 Asynchronous Read (VA Transition Before AVD Low)
6.4 Asynchronous Read (VA Transition After AVD Low)
6.5 Asynchronous Write
6.6 8-Word Linear Burst Write Mode
6.7 Burst Write Operation followed by Burst Read
6.8 Start Initial Burst Write Operation
6.9 Load Operation Timing
6.10 Superload Operation Timing
6.11 Program Operation Timing
6.12 Cache Program Operation Timing
......
Status
Ongoing
INT
ADQ15
{ {
6.14 Block Erase Operation Timing
6.15 Cold Reset Timing
6.16 Warm Reset Timing
6.17 Hot Reset Timing
RDY Operation or Idle Flex-MuxOneNAND reset Idle
Flex-MuxOneNAND Operation
6.18 NAND Flash Core Reset Timing
6.19 Data Protection Timing During Power Down
6.20 Toggle Bit Timing in Asynchronous Read (VA Transition Before AVD Low)
6.21 Toggle Bit Timing in Asynchronous Read (VA Transition After AVD Low)
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7.0 TECHNICAL AND APPLICATION NOTES
7.1 Methods of Determining Interrupt Status
7.1.1 The INT Pin to a Host General Purpose I/O
INT
COMMAND
7.1.2 Polling the Interrupt Register Status Bit
INT
7.1.3 Determining Rp Value (DDP, QDP Only)
INT pol = High (Default)
INT pol = Low
7.2 Boot Sequence
7.2.1 Boot Loaders in Flex-MuxOneNAND
7.2.2 Boot Sequence
Partition of NAND Flash array
Internal BufferRAM
NAND Flash Array
Flex-MuxOneNAND Boot Sequence
7.3 Partition of Flex-MuxOneNAND
{
{
{
: :
7.4 DDP and QDP Description
DDP(Dual Die Package):
QDP(Quad Die Package):
8.0 PACKAGE DIMENSIONS (TBD)
4G product (KFM4GH6Q4M)
8G product (KFN8GH6Q4M)
16G product (KFKAGH6Q4M)
