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Samsung KFKAGH6Q4M, KFN8GH6Q4M, KFM4GH6Q4M External BufferRAM Memory, Internal Nand Array Memory

Models: KFN8GH6Q4M KFM4GH6Q4M KFKAGH6Q4M

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Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)	FLASH MEMORY

2.6.2 External (BufferRAM) Memory Organization

The on-chip external memory is comprised of 3 buffers used for Boot Code storage and data buffering.

The BootRAM is a buffer that receives Boot Code from the internal memory and makes it available to the host at start up.

There are 4KB bi-directional data buffers(2KB x2), DataRAM0 and DataRAM1. During Boot Up, the BootRam is used by the host to initialize the main memory, and deliver boot code from NAND Flash core to host.

Host

External (BufferRAM)

Memory

BootRAM (1KB)

DataRAM0 (2KB)

DataRAM1 (2KB)

Internal (Nand Array)

Memory

Boot code

Nand Array

OTP Block

The external memory is divided into a main area and a spare area. Each buffer is the equivalent size of a Sector. The main area data is 512B. The spare area data is 16B.

External Memory Array Information

Area			BootRAM	DataRAM0	DataRAM1
Total Size			1KB+32B	2KB+64B	2KB+64B

Number of Sectors			2	4	4

Sector	Main		512B	512B	512B

	Spare		16B	16B	16B
	Spare		16B	16B	16B

External Memory Array Organization
			Main area data	Spare area data
			(512B)	(16B)

{ {

BootRAM

DataRAM0

DataRAM1

BootRAM 0

BootRAM 1

DataRAM 0_0

DataRAM 0_1

DataRAM 0_2

DataRAM 0_3

DataRAM 1_0

DataRAM 1_1

DataRAM 1_2

DataRAM 1_3

Sector: (512 + 16) Byte

4KByte

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Samsung KFKAGH6Q4M Internal Nand Array Memory, External BufferRAM Memory Organization, Boot code Nand Array OTP Block

Contents

KFM4GH6Q4M KFN8GH6Q4M KFKAGH6Q4M Revision No History Draft Date Initial issueRemark Corrected errataOct Ordering Information General Overview Device Architecture Product FeaturesDevice Performance System HardwareDefinitions Detailed Product Description1 4Gb KFM4GH6Q4M / 8Gb KFN8GH6Q4M Pin Configuration63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA4Gb TOP VIEW, Balls Facing Down 63ball Fbga OneNAND Chip 2 16Gb Product KFKAGH6Q4M TBDMultiplexed Address/Data bus Pin DescriptionRegister read cycles InterruptMemory Array Organization Block DiagramInternal Nand Array Memory Organization OTPBlockMLC SectorBlockSLC Boot code Nand Array OTP Block BootRAM 1KB DataRAM0 2KB DataRAM1 2KBExternal BufferRAM Memory Internal Nand Array MemoryBlock Block Address Size Memory Map0000h 256KBBlock Block Address Block160 Block128Block129 Block161Block240 00F0h Block238 00EEhBlock288 0120h Block257 Block256Block289 0121h Block258 Block290 0122h Block259Block352 0160h Block321 Block320Block353 0161h Block322 Block354 0162h Block323Block416 Block384Block385 Block417Block496 01F0h Block494 01EEhBlock544 0220h Block513 Block512Block545 0221h Block514 Block546 0222h Block515Block608 0260h Block577 Block576Block609 0261h Block578 Block610 0262h Block579Block672 Block640Block641 Block673Block752 02F0h Block750 02EEhBlock800 0320h Block769 Block768Block801 0321h Block770 Block802 0322h Block771Block864 0360h Block833 Block832Block865 0361h Block834 Block866 0362h Block835Block928 Block896Block897 Block929Block1008 03F0h Block1006 03EEhArea Internal Memory Spare Area Assignment256W ByteDivision Address Size Usage Description External Memory BufferRAM Address MapBootRAMSpare area BootRAMMain areaExternal Memory Map Detail Information DataRAMMain areaBuf Word Byte External Memory Spare Area Assignment10074h 803Bh 10076h 803Ch 10078h 803Dh 10054h 802Bh 10056h 802Ch 10058h 802Dh4bit ECC parity values 8046h 1008Ch 8047h 1008Eh 10090h BIBad block Information DataS10092h Managed by internal ECC logic 10094h 804Bh 10096h 804Ch 10098h 804DhRegister Address Map RegistersAddress Name Host Description Manufacturer ID Register F000h R Device ID DefaultDevice ID Register F001h R Device IdentificationData Buffer Size Register F003h R Version ID Register F002hThis register is reserved for future use Amount of Buffers Register F005h R Boot Buffer Size Register F004h RTechnology Register F006h R Start Address2 Register F101h R/W Start Address1 Register F100h R/W11~15 Start Address3~7 Register F102h~F106h Start Buffer Register F200h R/W Start Address8 Register F107h R/WBSC =111 Sector allocation according to BSCCASE1 FSA=00 BSC =Sector allocation according to BSCCASE2 FSA=01 BSC = Sector allocation according to BSCCASE3 FSA=10 BSC =Acceptable Command Register F220h R/WCMD OperationWrite command into INT will automatically Two Methods to Clear Interrupt Register in Command InputInterrupt Register Brwl System Configuration 1 Register F221h R, R/WBurst LengthMain Burst LengthSpare Burst Length BLBurst Length BL Information119 RDY Polarity RDYpol Information7Iobe Write Mode Information1 Definition Description Write Mode WMMRSMode Register Setting Description BwpsController Status Register F240h R System Configuration 2 Register F222hPIL Otpl OtpblOtpl INT Interrupt Status Register F241h R/WRsti EI Interrupt Status Conditions Default State Valid WI Interrupt Status Conditions Default State ValidRead Interrupt RI RI Interrupt Status ConditionsStart Block Address Register F24Dh R/W Start Block Address Register F24Ch R/WNand Flash Write Protection Status Register F24Eh R SBAECC Status Register 3 FF02h R FF02h, default = 0000h ECC Status Register 2 FF01h R FF01h, default = 0000hECC Status Register 4 FF03h R FF03h, default = 0000h ECC Status Register 1 FF00h RReset Flex-MuxOneNAND Add BP1 Data 00F0h Command Based OperationAdd Data 00E0h 0000h3 Read Identification Data XXXXh4 0090h Load Data Into Buffer Command Reset Flex-MuxOneNAND CommandRead Identification Data Command Identification Data Description Address Data OutOperation ADQ0~15 Device Bus OperationCLK AVD BP-F0h Reset Mode OperationWarm Reset Mode Operation Cold Reset Mode OperationHot Reset Mode Operation Nand Flash Core Reset Mode OperationWrite Protection Operation BootRAM Write Protection OperationNand Flash Array Write Protection Operation Nand Array Write Protection StatesUnlocked All Block Unlock Command Sequence Unlocked Unlock Command SequenceLocked Lock Command Sequence Unlocked Nand Array Write Protection StateLocked-tight Lock-Tight Command Sequence Nand Flash Array Write Protection State DiagramStart block address+Lock-tight block command 002Ch Locked-tight Nand Array Write Protection StateLock/Unlock/Lock-TightError completed Samsung strongly recommends to follow the above flow chartDBS, DFS is for DDP DQ10=0?All Block Unlock Completed Load Operation Data Protection During Power Down OperationSuperload Operation LSB Page Recovery Read Synchronous Read Mode Operation RM=1, WM=X Asynchronous Read Mode Operation RM=0, WM=0Read Operation 2.2 4-, 8-, 16-, 32-Word Linear Burst Read Operation Continuous Linear Burst Read OperationReserved area is not available on Synchronous read Programmable Burst Read Latency Operation Output Disable Mode OperationHandshaking Operation Synchronous WriteRM=1, WM=1 See Timing Diagram 6.6, 6.7Addressing for program operation Program OperationData register MLC BlockPaired Page Address Paired Page Address InformationFlash Memory Block including the page in error and copy If program operation results in an error, map outDBS, DFS is for DDP Target data to another block Interrupt register must not be written Program Interleave can work in Auto INTDBS, DFS is for DDP Sector0 Sector7 Cache Program OperationProgram Error Cache Program Operation Flow DiagramLast PGM? Add F101h DQ=DBS Add DataRAM DQ=Data4KBInterleave Cache Program Operation If program operation Results in an errorBlock Copy-Back Program Operation with Random Data Input Copy back completed Copy back ErrorAdd F241h DQ=0000h DQ=Data Write ‘DFS , FBA’ o f Fla shErase Operation Erase ErrorBlock Erase Operation INT=1Ready Erase Error Erase Interleave1 @DDP Flow ChartAdd F100h DQ=DFS*, FBA Add F101h DQ=DBS Add F101h DQ=DBS Add F241h DQ=5=EIErase Suspend During a Block Erase Operation Erase Suspend / Erase Resume OperationErase Resume Partition Information PI Block SLC Only PI Block Boundary Information setting steps PI Block Boundary Information settingPI Block Boundary Information setting Flow Chart PI Block Access mode entry Flow Chart PI Block Access mode entryPI Block Erase PI Block Erase Operation Flow Chart In PI Block Access ModeErasing the PI Area Memory location in the PI area can be program PI Block Program OperationProgramming the PI Area Locking the PIUpdate the PI Area PI UpdateAdd F241h DQ15=INT PI updated PI Block Load Operation OTP Operation SLC only 1st Block OTP Area Structure OTP Block Area StructureOTP Exit OTP Block Load OperationProgramming the OTP Area OTP Block Program OperationDo Cold/Warm/Hot Nand Flash Core reset OTP Exit OTP Block Program Operation Flow ChartAdd DP DQ=Data-in OTPL=0? YESLocking the OTP OTP Block Lock OperationOTP Lock Operation Steps Automatically Updated Add F241h DQ15=INT Do Cold resetAdd F241h DQ15=INT Write Data into DataRAM3 Add 1st Word Locking the 1st Block OTP 13.4 1st Block OTP Lock Operation1st Block OTP Lock Operation Steps 100 Locking the OTP and 1st Block OTP OTP and 1st Block OTP Lock OperationOTP and 1st Block OTP simultaneous Lock Operation Steps 102 Status DQ15~DQ7 14 DQ6 Toggle BitDQ6 DQ5~DQ0 Progress Data Loading Don’t CareECC Bypass Operation ECC OperationInvalid Block Identification Table Operation Invalid Block OperationInvalid Block Table Creation Flow Chart Start Invalid Block Replacement OperationBlock a Block Replacement Operation Sequence1st 1th Nth 1st Block B 1th Nth 107Operating Conditions Absolute Maximum RatingsKFM4GH6Q4M Parameter DC CharacteristicsTest Conditions AC Test Conditions Valid Block CharacteristicsDevice Capacitance DDP QDPSee Timing Diagrams 6.1 Parameter AC Characteristics for Synchronous Burst Read66MHz 83MHz Unit Max MinKFN8GH6Q4M AC Characteristics for Asynchronous ReadKFKAGH6Q4MTBD Min MaxAC Characteristics for Burst Write Operation AC Characteristics for Asynchronous WriteSee Timing Diagrams Parameter Symbol Min Max Unit AC Characteristics for INT Auto Mode AC Characteristics for Load/Program/Erase Performance200 114Continuous Linear Burst Read Mode with Wrap Around 8-Word Linear Burst Read Mode with Wrap AroundCLK RDYAsynchronous Read VA Transition Before See AC Characteristics Table DQ0 DQ15Low Asynchronous Read VA Transition After AVD LowADQ15-ADQ0 Asynchronous WriteValid WD Hi-ZBurst Write Operation followed by Burst Read 8-Word Linear Burst Write Mode≈D7 118119 Start Initial Burst Write OperationLoad Command Sequence last two cycles Read Data See AC Characteristics .7 and TableLoad Operation Timing Completed Da+nSuperload Operation Timing Program Operation Timing Program Command Sequence last two cycles122 Ongoing Status TimingADQ0~ Interleave Cache Program OperationADQ15 Ongoing Status INT bitBlock Erase Operation Timing Erase Command Sequence125 Cold Reset Timing CE, OE Warm Reset Timing127 Flex-MuxOneNAND Hot Reset TimingADQi Data Protection Timing During Power Down Nand Flash Core Reset TimingFlex-MuxOneNAND Operation or Idle Nand Flash Core reset ADQiRDY Status RD Hi-Z130 Write command into Command Register INT will automatically INT auto mode131 INT Type Mono INT Type DDP Methods of Determining Interrupt StatusGeneral Operation DQ type 132Asynchronous Mode Using the INT Pin Synchronous Mode Using the INT PinINT Pin to a Host General Purpose I/O 134 Polling the Interrupt Register Status BitDetermining Rp Value DDP, QDP Only INT pol = ‘High’ DefaultRpohm Vcc or Vccq INT pol = ‘Low’Ready Vss KFN8GH6Q4M @ Vcc = 1.8V, Ta = 25C , CL = 30pFBoot Loaders in Flex-MuxOneNAND Boot SequenceBoot Sequence Boot Loaders in Flex-MuxOneNAND DescriptionBL2 NBL3BL1 NBL2MLC Partition +1 ~ n-1 Blocks Partition of Flex-MuxOneNANDLast Block Address First Block Address Data RegisterDDPDual Die Package DDP and QDP DescriptionQDPQuad Die Package 8G product KFN8GH6Q4M 4G product KFM4GH6Q4M141 142 16G product KFKAGH6Q4M