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Samsung KFN8GH6Q4M, KFKAGH6Q4M, KFM4GH6Q4M warranty NBL3, NBL2, BL1 BL2, Dram

Models: KFN8GH6Q4M KFM4GH6Q4M KFKAGH6Q4M

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Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)	FLASH MEMORY

	Block 1023
		Reservoir
	File System
	Block 162
		Os Image
	Block 2	NBL3
	Block 1	NBL3
	Block 1	BL2
	BL1	BL2
	BL1	NBL2
	Block 0

Partition 6

Partition 5

Partition 4

Partition 3

BL2

Sector0 Sector1 Sector2 Sector3 Sector4 Sector5 Sector6 Sector7

	Page 63
	Page 62
	:
	:
	Page 2
	Page 1
BL1	Page 0

Partition of NAND Flash array

	Reservoir
File System
	Os Image	DataRam(4KB)
BL1	BL2	Boot Ram(BL 1)
BL1	BL2
		step 1

NAND Flash Array

Internal BufferRAM

step 3

step 2

Os Image

BL 2

Flex-MuxOneNAND

DRAM

Flex-MuxOneNAND Boot Sequence

NOTE : 1) Step 2 and Step 3 can be copied into DRAM through two DataRAMs.

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Image 138

Samsung KFN8GH6Q4M, KFKAGH6Q4M, KFM4GH6Q4M warranty NBL3, NBL2, BL1 BL2, Dram

Contents

KFM4GH6Q4M KFN8GH6Q4M KFKAGH6Q4M Remark Initial issueRevision No History Draft Date Corrected errataOct Ordering Information General Overview Device Performance Product FeaturesDevice Architecture System HardwareDetailed Product Description DefinitionsPin Configuration 1 4Gb KFM4GH6Q4M / 8Gb KFN8GH6Q4M63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA4Gb 2 16Gb Product KFKAGH6Q4M TBD TOP VIEW, Balls Facing Down 63ball Fbga OneNAND ChipRegister read cycles Pin DescriptionMultiplexed Address/Data bus InterruptInternal Nand Array Memory Organization Block DiagramMemory Array Organization OTPSector BlockMLCBlockSLC External BufferRAM Memory BootRAM 1KB DataRAM0 2KB DataRAM1 2KBBoot code Nand Array OTP Block Internal Nand Array Memory0000h Memory MapBlock Block Address Size 256KBBlock Block Address Block129 Block128Block160 Block161Block238 00EEh Block240 00F0hBlock289 0121h Block258 Block256Block288 0120h Block257 Block290 0122h Block259Block353 0161h Block322 Block320Block352 0160h Block321 Block354 0162h Block323Block385 Block384Block416 Block417Block494 01EEh Block496 01F0hBlock545 0221h Block514 Block512Block544 0220h Block513 Block546 0222h Block515Block609 0261h Block578 Block576Block608 0260h Block577 Block610 0262h Block579Block641 Block640Block672 Block673Block750 02EEh Block752 02F0hBlock801 0321h Block770 Block768Block800 0320h Block769 Block802 0322h Block771Block865 0361h Block834 Block832Block864 0360h Block833 Block866 0362h Block835Block897 Block896Block928 Block929Block1006 03EEh Block1008 03F0h256W Internal Memory Spare Area AssignmentArea ByteExternal Memory BufferRAM Address Map Division Address Size Usage DescriptionExternal Memory Map Detail Information BootRAMMain areaBootRAMSpare area DataRAMMain areaExternal Memory Spare Area Assignment Buf Word Byte10054h 802Bh 10056h 802Ch 10058h 802Dh 10074h 803Bh 10076h 803Ch 10078h 803Dh4bit ECC parity values 8046h 1008Ch 8047h 1008Eh 10092h Managed by internal ECC logic DataS10090h BIBad block Information 10094h 804Bh 10096h 804Ch 10098h 804DhRegisters Register Address MapAddress Name Host Description Device ID Register F001h R Device ID DefaultManufacturer ID Register F000h R Device IdentificationVersion ID Register F002h Data Buffer Size Register F003h RThis register is reserved for future use Boot Buffer Size Register F004h R Amount of Buffers Register F005h RTechnology Register F006h R Start Address1 Register F100h R/W Start Address2 Register F101h R/W11~15 Start Address3~7 Register F102h~F106h Start Address8 Register F107h R/W Start Buffer Register F200h R/WSector allocation according to BSCCASE2 FSA=01 BSC = Sector allocation according to BSCCASE1 FSA=00 BSC =BSC =111 Sector allocation according to BSCCASE3 FSA=10 BSC =CMD Command Register F220h R/WAcceptable OperationTwo Methods to Clear Interrupt Register in Command Input Write command into INT will automaticallyInterrupt Register System Configuration 1 Register F221h R, R/W BrwlBurst Length BL Information119 Burst Length BLBurst LengthMain Burst LengthSpare RDY Polarity RDYpol Information7Iobe MRSMode Register Setting Description Write Mode WMWrite Mode Information1 Definition Description BwpsPIL System Configuration 2 Register F222hController Status Register F240h R Otpl OtpblOtpl Interrupt Status Register F241h R/W INTRsti Read Interrupt RI WI Interrupt Status Conditions Default State ValidEI Interrupt Status Conditions Default State Valid RI Interrupt Status ConditionsNand Flash Write Protection Status Register F24Eh R Start Block Address Register F24Ch R/WStart Block Address Register F24Dh R/W SBAECC Status Register 4 FF03h R FF03h, default = 0000h ECC Status Register 2 FF01h R FF01h, default = 0000hECC Status Register 3 FF02h R FF02h, default = 0000h ECC Status Register 1 FF00h RCommand Based Operation Reset Flex-MuxOneNAND Add BP1 Data 00F0hAdd Data 00E0h 0000h3 Read Identification Data XXXXh4 0090h Read Identification Data Command Reset Flex-MuxOneNAND CommandLoad Data Into Buffer Command Identification Data Description Address Data OutDevice Bus Operation Operation ADQ0~15CLK AVD Reset Mode Operation BP-F0hHot Reset Mode Operation Cold Reset Mode OperationWarm Reset Mode Operation Nand Flash Core Reset Mode OperationNand Flash Array Write Protection Operation BootRAM Write Protection OperationWrite Protection Operation Nand Array Write Protection StatesLocked Lock Command Sequence Unlocked Unlock Command SequenceUnlocked All Block Unlock Command Sequence Unlocked Nand Array Write Protection StateStart block address+Lock-tight block command 002Ch Nand Flash Array Write Protection State DiagramLocked-tight Lock-Tight Command Sequence Locked-tight Nand Array Write Protection StateDBS, DFS is for DDP Samsung strongly recommends to follow the above flow chartLock/Unlock/Lock-TightError completed DQ10=0?All Block Unlock Completed Data Protection During Power Down Operation Load OperationSuperload Operation LSB Page Recovery Read Asynchronous Read Mode Operation RM=0, WM=0 Synchronous Read Mode Operation RM=1, WM=XRead Operation Continuous Linear Burst Read Operation 2.2 4-, 8-, 16-, 32-Word Linear Burst Read OperationReserved area is not available on Synchronous read Output Disable Mode Operation Programmable Burst Read Latency OperationHandshaking Operation See Timing Diagram 6.6, 6.7 Synchronous WriteRM=1, WM=1Data register Program OperationAddressing for program operation MLC BlockPaired Page Address Information Paired Page AddressFlash Memory If program operation results in an error, map out Block including the page in error and copyDBS, DFS is for DDP Target data to another block Program Interleave can work in Auto INT Interrupt register must not be writtenDBS, DFS is for DDP Cache Program Operation Sector0 Sector7Last PGM? Cache Program Operation Flow DiagramProgram Error Add F101h DQ=DBS Add DataRAM DQ=Data4KBInterleave Cache Program Operation Results in an error If program operationBlock Add F241h DQ=0000h DQ=Data Copy back completed Copy back ErrorCopy-Back Program Operation with Random Data Input Write ‘DFS , FBA’ o f Fla shErase Error Erase OperationBlock Erase Operation Add F100h DQ=DFS*, FBA Add F101h DQ=DBS Erase Interleave1 @DDP Flow ChartINT=1Ready Erase Error Add F101h DQ=DBS Add F241h DQ=5=EIErase Suspend / Erase Resume Operation Erase Suspend During a Block Erase OperationErase Resume Partition Information PI Block SLC Only PI Block Boundary Information setting PI Block Boundary Information setting stepsPI Block Boundary Information setting Flow Chart PI Block Access mode entry PI Block Access mode entry Flow ChartPI Block Erase Operation Flow Chart In PI Block Access Mode PI Block EraseErasing the PI Area Programming the PI Area PI Block Program OperationMemory location in the PI area can be program Locking the PIPI Update Update the PI AreaAdd F241h DQ15=INT PI updated PI Block Load Operation OTP Operation SLC only OTP Block Area Structure 1st Block OTP Area StructureOTP Block Load Operation OTP ExitOTP Block Program Operation Programming the OTP AreaAdd DP DQ=Data-in OTP Block Program Operation Flow ChartDo Cold/Warm/Hot Nand Flash Core reset OTP Exit OTPL=0? YESOTP Block Lock Operation Locking the OTPOTP Lock Operation Steps Add F241h DQ15=INT Do Cold reset Automatically UpdatedAdd F241h DQ15=INT Write Data into DataRAM3 Add 1st Word 13.4 1st Block OTP Lock Operation Locking the 1st Block OTP1st Block OTP Lock Operation Steps 100 OTP and 1st Block OTP Lock Operation Locking the OTP and 1st Block OTPOTP and 1st Block OTP simultaneous Lock Operation Steps 102 DQ6 DQ5~DQ0 14 DQ6 Toggle BitStatus DQ15~DQ7 Progress Data Loading Don’t CareECC Operation ECC Bypass OperationInvalid Block Operation Invalid Block Identification Table OperationInvalid Block Replacement Operation Invalid Block Table Creation Flow Chart Start1st 1th Nth Block Replacement Operation SequenceBlock a 1st Block B 1th Nth 107Absolute Maximum Ratings Operating ConditionsKFM4GH6Q4M DC Characteristics ParameterTest Conditions Device Capacitance Valid Block CharacteristicsAC Test Conditions DDP QDP66MHz 83MHz Unit AC Characteristics for Synchronous Burst ReadSee Timing Diagrams 6.1 Parameter Max MinKFKAGH6Q4MTBD AC Characteristics for Asynchronous ReadKFN8GH6Q4M Min MaxAC Characteristics for Asynchronous Write AC Characteristics for Burst Write OperationSee Timing Diagrams Parameter Symbol Min Max Unit 200 AC Characteristics for Load/Program/Erase PerformanceAC Characteristics for INT Auto Mode 114CLK 8-Word Linear Burst Read Mode with Wrap AroundContinuous Linear Burst Read Mode with Wrap Around RDYLow See AC Characteristics Table DQ0 DQ15Asynchronous Read VA Transition Before Asynchronous Read VA Transition After AVD LowValid WD Asynchronous WriteADQ15-ADQ0 Hi-Z≈D7 8-Word Linear Burst Write ModeBurst Write Operation followed by Burst Read 118Start Initial Burst Write Operation 119Load Operation Timing See AC Characteristics .7 and TableLoad Command Sequence last two cycles Read Data Completed Da+nSuperload Operation Timing Program Command Sequence last two cycles Program Operation Timing122 Timing Ongoing StatusADQ15 Interleave Cache Program OperationADQ0~ Ongoing Status INT bitErase Command Sequence Block Erase Operation Timing125 Cold Reset Timing Warm Reset Timing CE, OE127 Hot Reset Timing Flex-MuxOneNANDADQi Flex-MuxOneNAND Operation or Idle Nand Flash Core reset Nand Flash Core Reset TimingData Protection Timing During Power Down ADQiStatus RD Hi-Z RDY130 INT auto mode Write command into Command Register INT will automatically131 General Operation DQ type Methods of Determining Interrupt StatusINT Type Mono INT Type DDP 132Synchronous Mode Using the INT Pin Asynchronous Mode Using the INT PinINT Pin to a Host General Purpose I/O Polling the Interrupt Register Status Bit 134INT pol = ‘High’ Default Determining Rp Value DDP, QDP OnlyRpohm Ready INT pol = ‘Low’Vcc or Vccq Vss KFN8GH6Q4M @ Vcc = 1.8V, Ta = 25C , CL = 30pFBoot Sequence Boot SequenceBoot Loaders in Flex-MuxOneNAND Boot Loaders in Flex-MuxOneNAND DescriptionBL1 NBL3BL2 NBL2Last Block Address First Block Address Partition of Flex-MuxOneNANDMLC Partition +1 ~ n-1 Blocks Data RegisterDDP and QDP Description DDPDual Die PackageQDPQuad Die Package 4G product KFM4GH6Q4M 8G product KFN8GH6Q4M141 16G product KFKAGH6Q4M 142

FLASH MEMORY

NBL3

BL2

BL1

NBL2

Partition of NAND Flash array

BL1

BL2

DRAM