Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
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FLASH MEMORY
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
Interleave Cache Program Operation Flow Diagram
NOTE :
1) DBS must be set before data input.
2) FSA must be 00 and BSC must be 000 within program operation.
3) BSA must be 1000.
4) Writing System Configuration Register is optional.
5) Host is strongly recommended to see the INT register(F241h) of each chip.
6) Once ‘PGM command’ is issued onto a chip, the same command(PGM) must be issued onto another chip. If not, Samsung cannot gurantee the following oper-
ation.
7) If error bit is set at this step, DQ[1]~[4] shoulde be checked in order to find where the error occurred.
Start
Write ‘DFS, FBA’ of Flash
Add: F100h DQ=DFS, FBA
Select DataRAM for DDP
1)
Add: F101h DQ=DBS
Check INT register
Add: F241h DQ=8040h
complete
Program Error
if it is ready
5)
Write ‘FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
2)
Write Data into DataRAM0,1
Add: DataRAM DQ=Data(4KB)
Write Cache PGM CMD
Add: F220h DQ=007Fh
Add: F240h
Read Controller
Status Register
Is it first input
for a chip
Select a chip for DDP
1)
Add: F100h DQ=DFS
DQ[4] | DQ[2] = 0?
Last PGM
for a chip?
Write ‘DFS, FBA’ of Flash
Add: F100h DQ=DFS, FBA
Write ‘FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
2)
Write Data into DataRAM0,1
Add: DataRAM DQ=Data(4KB)
Write PGM CMD
6)
Add: F220h DQ=0080h
Write ‘DFS, FBA’ of Flash
Add: F100h DQ=DFS, FBA
Write ‘FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
2)
Write Data into DataRAM0,1
Add: DataRAM DQ=Data(4KB)
Write PGM CMD
6)
Add: F220h DQ=0080h
Check INT register
Add: F241h DQ=8040h
if it is ready
3)
DQ[4] | DQ[2] = 0?
DQ[10]=0?
Wait for INT register
Add: F241h DQ=8040h
low to high transition
5)
Add: F240h DQ[10]=Error
Read Controller
Status Register
7)
Select DataRAM for DDP
1)
Add: F101h DQ=DBS
Check INT register
Add: F241h DQ=8040h
if it is ready
5)
DQ[10]=0?
Add: F240h DQ[10]=Error
Read Controller
Status Register
7)
YES
NO
YES
YES
NO
NO
YES
NO
YES
NO
YES
NO
* DBS, DFS is for DDP
*If program operation
results in an error,
map out the block
including the page in
error and copy the
target data to an other
block.
DQ[2]=Previous
Add: F240h
Read Controller
Status Register
DQ[2]=Previous
Write ‘BSA3), BSC’ of DataRAM
Add: F200h DQ=0800h2)
Add: F101h DQ=DBS
Select a chip for DDP
1)
Add: F100h DQ=DFS
Add: F101h DQ=DBS
Read Write Protection Status
Add: F24Eh DQ=US,LS,LTS
Write System Configuration
Add: F221h DQ=ECC
Register4)
Read Write Protection Status
Add: F24Eh DQ=US,LS,LTS
Add: F221h DQ=ECC
Register4)
Write System Configuration
Read Write Protection Status
Add: F24Eh DQ=US,LS,LTS
Write System Configuration
Add: F221h DQ=ECC
Register4)