Samsung KFN8GH6Q4M AC Characteristics for Synchronous Burst Read, 66MHz 83MHz Unit, Max Min

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)											FLASH MEMORY
5.4 AC Characteristics for Synchronous Burst Read
				See Timing Diagrams 6.1 and 6.2
						Parameter	Symbol	66MHz			83MHz		Unit
								Min	Max	Min		Max
	Clock						CLK	1	66	1		83	MHz
	Clock Cycle						tCLK	15	-	12		-	ns
	Initial Access Time						tIAA	-	70	-		70	ns
	Burst Access Time Valid Clock to Output Delay						tBA	-	11	-		9	ns
				Setup Time to CLK			tAVDS	5	-	4		-	ns
	AVD
				Hold Time from CLK			tAVDH	2	-	2		-	ns
	AVD
				High to		Low	tAVDO	0	-	0		-	ns
	AVD				OE
	Address Setup Time to CLK						tACS	5	-	4		-	ns
	Address Hold Time from CLK						tACH	6	-	6		-	ns
	Data Hold Time from Next Clock Cycle						tBDH	3	-	2		-	ns
	Output Enable to Data						tOE	-	20	-		20	ns
			Disable to Output & RDY High Z				tCEZ1)	-	20	-		20	ns
	CE
			Disable to Output High Z				tOEZ1)	-	15	-		15	ns
	OE
		Setup Time to CLK					tCES	6	-	4.5		-	ns
	CE
	CLK High or Low Time						tCLKH/L	tCLK/3	-	5		-	ns
	CLK 2) to RDY valid						tRDYO	-	11	-		9	ns
	CLK to RDY Setup Time						tRDYA	-	11	-		9	ns
	RDY Setup Time to CLK						tRDYS	4	-	3		-	ns
		low to RDY valid					tCER	-	15	-		15	ns
	CE

NOTE :

1)If OE is disabled at the same time or before CE is disabled, the output will go to high-z by tOEZ. If CE is disabled at the same time or before OE is disabled, the output will go to high-z by tCEZ. If CE and OE are disabled at the same time, the output will go to high-z by tOEZ.

2)It is the following clock of address fetch clock.

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