Samsung warranty AC Characteristics for Asynchronous Read, KFN8GH6Q4M, KFKAGH6Q4MTBD, Min Max

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)	FLASH MEMORY

5.5 AC Characteristics for Asynchronous Read

See Timing Diagrams 6.3 and 6.4.

KFM4GH6Q4M/

Parameter

Symbol

KFN8GH6Q4M/

Unit

KFKAGH6Q4M(TBD)

Min

Max

Access Time from

Low

tCE

-

76

ns

CE

Asynchronous Access Time from

Low

tAA

-

76

ns

AVD

Asynchronous Access Time from address valid

tACC

-

76

ns

Read Cycle Time

tRC

76

-

ns

Low Time

tAVDP

12

-

ns

AVD

Address Setup to rising edge of

tAAVDS

5

-

ns

AVD

Address Hold from rising edge of

tAAVDH

6

-

ns

AVD

Output Enable to Output Valid

tOE

-

20

ns

Setup to

falling edge

tCA

0

-

ns

CE

AVD

Disable to Output & RDY High Z1)

tCEZ

-

20

ns

CE

Disable to Output High Z1)

tOEZ

-

15

ns

OE

High to

Low

tAVDO

0

-

ns

AVD

OE

Low to RDY Valid

tCER

-

15

ns

CE

Disable to

Enable

tWEA

15

-

ns

WE

AVD

Address to

low

tASO2)

10

-

ns

OE

NOTE :

1)If OE is disabled at the same time or before CE is disabled, the output will go to high-z by tOEZ. If CE is disabled at the same time or before OE is disabled, the output will go to high-z by tCEZ. If CE and OE are disabled at the same time, the output will go to high-z by tOEZ.

These parameters are not 100% tested.

2)This Parameter is valid at toggle bit timing in asynchronous read only. (timing diagram 6.20 and 6.21)

5.6 AC Characteristics for Warm Reset (RP), Hot Reset and NAND Flash Core Reset

See Timing Diagrams 6.16, 6.17 and 6.18.

	Parameter	Symbol	Min	Max	Unit
		tReady1	-	5
RP & Reset Command Latch to BootRAM Access					∝s
		(BufferRAM)
		tReady2	-	10
RP & Reset Command Latch(During Load Routines) to INT High (Note1)					∝s
		(NAND Flash Array)
		tReady2	-	20
RP & Reset Command Latch(During Program Routines) to INT High (Note1)					∝s
		(NAND Flash Array)
		tReady2	-	150
RP & Reset Command Latch(During Erase Routines) to INT High (Note1)					∝s
		(NAND Flash Array)
		tReady2	-	10
RP & Reset Command Latch(NOT During Internal Routines) to INT High (Note1)					∝s
		(NAND Flash Array)
	Pulse Width (Note2)		200	-	ns
RP		tRP

NOTE :

1)These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and pull-down resistor value.

2)The device may reset if tRP < tRP min(200ns), but this is not guaranteed.

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