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Samsung KFN8GH6Q4M Load Operation Timing, See AC Characteristics .7 and Table, Completed Da+n

Models: KFN8GH6Q4M KFM4GH6Q4M KFKAGH6Q4M

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Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)	FLASH MEMORY

6.9 Load Operation Timing

See AC Characteristics Table 5.7 and Table 5.9

tAAVDS	Load Command Sequence (last two cycles)		Read Data
tAAVDS		tWEA

AVD

	tAVDP
		tAAVDH
ADQ0~15	AA	LMA	CA	LCD	≈	SA	Completed	BA	Da+n
ADQ0~15	AA	LMA	CA	LCD	≈	SA	Completed	BA	Da+n
				tDS	≈
	tCS			tDS
	tCS			tDH	≈
CE				tDH


	tCER				tCER
	tCER				≈
OE				tCH	≈
				tCH

		tWPL
WE					≈
WE			tWPH
			tWPH	tRD1 or tRD2
				tRD1 or tRD2
		tWC
CLK		VIL			≈
CLK					≈
INT
bit
	Hi-Z			tCEZ					tCEZ
RDY	Hi-Z
RDY

NOTE :

1)AA = Address of address register CA = Address of command register LCD = Load Command

LMA = Address of memory to be loaded

BA = Address of BufferRAM to load the data SA = Address of status register

2)“In progress” and “complete” refer to status register

3)Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

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Samsung KFN8GH6Q4M, KFKAGH6Q4M, KFM4GH6Q4M Load Operation Timing, See AC Characteristics .7 and Table, Completed Da+n, 120

Contents

KFM4GH6Q4M KFN8GH6Q4M KFKAGH6Q4M Initial issue Revision No History Draft DateRemark Corrected errataOct Ordering Information General Overview Product Features Device ArchitectureDevice Performance System HardwareDetailed Product Description DefinitionsPin Configuration 1 4Gb KFM4GH6Q4M / 8Gb KFN8GH6Q4M63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA4Gb 2 16Gb Product KFKAGH6Q4M TBD TOP VIEW, Balls Facing Down 63ball Fbga OneNAND ChipPin Description Multiplexed Address/Data busRegister read cycles InterruptBlock Diagram Memory Array OrganizationInternal Nand Array Memory Organization OTPSector BlockMLCBlockSLC BootRAM 1KB DataRAM0 2KB DataRAM1 2KB Boot code Nand Array OTP BlockExternal BufferRAM Memory Internal Nand Array MemoryMemory Map Block Block Address Size0000h 256KBBlock Block Address Block128 Block160Block129 Block161Block238 00EEh Block240 00F0hBlock256 Block288 0120h Block257Block289 0121h Block258 Block290 0122h Block259Block320 Block352 0160h Block321Block353 0161h Block322 Block354 0162h Block323Block384 Block416Block385 Block417Block494 01EEh Block496 01F0hBlock512 Block544 0220h Block513Block545 0221h Block514 Block546 0222h Block515Block576 Block608 0260h Block577Block609 0261h Block578 Block610 0262h Block579Block640 Block672Block641 Block673Block750 02EEh Block752 02F0hBlock768 Block800 0320h Block769Block801 0321h Block770 Block802 0322h Block771Block832 Block864 0360h Block833Block865 0361h Block834 Block866 0362h Block835Block896 Block928Block897 Block929Block1006 03EEh Block1008 03F0hInternal Memory Spare Area Assignment Area256W ByteExternal Memory BufferRAM Address Map Division Address Size Usage DescriptionBootRAMMain area BootRAMSpare areaExternal Memory Map Detail Information DataRAMMain areaExternal Memory Spare Area Assignment Buf Word Byte10054h 802Bh 10056h 802Ch 10058h 802Dh 10074h 803Bh 10076h 803Ch 10078h 803Dh4bit ECC parity values 8046h 1008Ch 8047h 1008Eh DataS 10090h BIBad block Information10092h Managed by internal ECC logic 10094h 804Bh 10096h 804Ch 10098h 804DhRegisters Register Address MapAddress Name Host Description Device ID Default Manufacturer ID Register F000h RDevice ID Register F001h R Device IdentificationVersion ID Register F002h Data Buffer Size Register F003h RThis register is reserved for future use Boot Buffer Size Register F004h R Amount of Buffers Register F005h RTechnology Register F006h R Start Address1 Register F100h R/W Start Address2 Register F101h R/W11~15 Start Address3~7 Register F102h~F106h Start Address8 Register F107h R/W Start Buffer Register F200h R/WSector allocation according to BSCCASE1 FSA=00 BSC = BSC =111Sector allocation according to BSCCASE2 FSA=01 BSC = Sector allocation according to BSCCASE3 FSA=10 BSC =Command Register F220h R/W AcceptableCMD OperationTwo Methods to Clear Interrupt Register in Command Input Write command into INT will automaticallyInterrupt Register System Configuration 1 Register F221h R, R/W BrwlBurst Length BL Burst LengthMain Burst LengthSpareBurst Length BL Information119 RDY Polarity RDYpol Information7Iobe Write Mode WM Write Mode Information1 Definition DescriptionMRSMode Register Setting Description BwpsSystem Configuration 2 Register F222h Controller Status Register F240h RPIL Otpl OtpblOtpl Interrupt Status Register F241h R/W INTRsti WI Interrupt Status Conditions Default State Valid EI Interrupt Status Conditions Default State ValidRead Interrupt RI RI Interrupt Status ConditionsStart Block Address Register F24Ch R/W Start Block Address Register F24Dh R/WNand Flash Write Protection Status Register F24Eh R SBAECC Status Register 2 FF01h R FF01h, default = 0000h ECC Status Register 3 FF02h R FF02h, default = 0000hECC Status Register 4 FF03h R FF03h, default = 0000h ECC Status Register 1 FF00h RCommand Based Operation Reset Flex-MuxOneNAND Add BP1 Data 00F0hAdd Data 00E0h 0000h3 Read Identification Data XXXXh4 0090h Reset Flex-MuxOneNAND Command Load Data Into Buffer CommandRead Identification Data Command Identification Data Description Address Data OutDevice Bus Operation Operation ADQ0~15CLK AVD Reset Mode Operation BP-F0hCold Reset Mode Operation Warm Reset Mode OperationHot Reset Mode Operation Nand Flash Core Reset Mode OperationBootRAM Write Protection Operation Write Protection OperationNand Flash Array Write Protection Operation Nand Array Write Protection StatesUnlocked Unlock Command Sequence Unlocked All Block Unlock Command SequenceLocked Lock Command Sequence Unlocked Nand Array Write Protection StateNand Flash Array Write Protection State Diagram Locked-tight Lock-Tight Command SequenceStart block address+Lock-tight block command 002Ch Locked-tight Nand Array Write Protection StateSamsung strongly recommends to follow the above flow chart Lock/Unlock/Lock-TightError completedDBS, DFS is for DDP DQ10=0?All Block Unlock Completed Data Protection During Power Down Operation Load OperationSuperload Operation LSB Page Recovery Read Asynchronous Read Mode Operation RM=0, WM=0 Synchronous Read Mode Operation RM=1, WM=XRead Operation Continuous Linear Burst Read Operation 2.2 4-, 8-, 16-, 32-Word Linear Burst Read OperationReserved area is not available on Synchronous read Output Disable Mode Operation Programmable Burst Read Latency OperationHandshaking Operation See Timing Diagram 6.6, 6.7 Synchronous WriteRM=1, WM=1Program Operation Addressing for program operationData register MLC BlockPaired Page Address Information Paired Page AddressFlash Memory If program operation results in an error, map out Block including the page in error and copyDBS, DFS is for DDP Target data to another block Program Interleave can work in Auto INT Interrupt register must not be writtenDBS, DFS is for DDP Cache Program Operation Sector0 Sector7Cache Program Operation Flow Diagram Program ErrorLast PGM? Add F101h DQ=DBS Add DataRAM DQ=Data4KBInterleave Cache Program Operation Results in an error If program operationBlock Copy back completed Copy back Error Copy-Back Program Operation with Random Data InputAdd F241h DQ=0000h DQ=Data Write ‘DFS , FBA’ o f Fla shErase Error Erase OperationBlock Erase Operation Erase Interleave1 @DDP Flow Chart INT=1Ready Erase ErrorAdd F100h DQ=DFS*, FBA Add F101h DQ=DBS Add F101h DQ=DBS Add F241h DQ=5=EIErase Suspend / Erase Resume Operation Erase Suspend During a Block Erase OperationErase Resume Partition Information PI Block SLC Only PI Block Boundary Information setting PI Block Boundary Information setting stepsPI Block Boundary Information setting Flow Chart PI Block Access mode entry PI Block Access mode entry Flow ChartPI Block Erase Operation Flow Chart In PI Block Access Mode PI Block EraseErasing the PI Area PI Block Program Operation Memory location in the PI area can be programProgramming the PI Area Locking the PIPI Update Update the PI AreaAdd F241h DQ15=INT PI updated PI Block Load Operation OTP Operation SLC only OTP Block Area Structure 1st Block OTP Area StructureOTP Block Load Operation OTP ExitOTP Block Program Operation Programming the OTP AreaOTP Block Program Operation Flow Chart Do Cold/Warm/Hot Nand Flash Core reset OTP ExitAdd DP DQ=Data-in OTPL=0? YESOTP Block Lock Operation Locking the OTPOTP Lock Operation Steps Add F241h DQ15=INT Do Cold reset Automatically UpdatedAdd F241h DQ15=INT Write Data into DataRAM3 Add 1st Word 13.4 1st Block OTP Lock Operation Locking the 1st Block OTP1st Block OTP Lock Operation Steps 100 OTP and 1st Block OTP Lock Operation Locking the OTP and 1st Block OTPOTP and 1st Block OTP simultaneous Lock Operation Steps 102 14 DQ6 Toggle Bit Status DQ15~DQ7DQ6 DQ5~DQ0 Progress Data Loading Don’t CareECC Operation ECC Bypass OperationInvalid Block Operation Invalid Block Identification Table OperationInvalid Block Replacement Operation Invalid Block Table Creation Flow Chart StartBlock Replacement Operation Sequence Block a1st 1th Nth 1st Block B 1th Nth 107Absolute Maximum Ratings Operating ConditionsKFM4GH6Q4M DC Characteristics ParameterTest Conditions Valid Block Characteristics AC Test ConditionsDevice Capacitance DDP QDPAC Characteristics for Synchronous Burst Read See Timing Diagrams 6.1 Parameter66MHz 83MHz Unit Max MinAC Characteristics for Asynchronous Read KFN8GH6Q4MKFKAGH6Q4MTBD Min MaxAC Characteristics for Asynchronous Write AC Characteristics for Burst Write OperationSee Timing Diagrams Parameter Symbol Min Max Unit AC Characteristics for Load/Program/Erase Performance AC Characteristics for INT Auto Mode200 1148-Word Linear Burst Read Mode with Wrap Around Continuous Linear Burst Read Mode with Wrap AroundCLK RDYSee AC Characteristics Table DQ0 DQ15 Asynchronous Read VA Transition BeforeLow Asynchronous Read VA Transition After AVD LowAsynchronous Write ADQ15-ADQ0Valid WD Hi-Z8-Word Linear Burst Write Mode Burst Write Operation followed by Burst Read≈D7 118Start Initial Burst Write Operation 119See AC Characteristics .7 and Table Load Command Sequence last two cycles Read DataLoad Operation Timing Completed Da+nSuperload Operation Timing Program Command Sequence last two cycles Program Operation Timing122 Timing Ongoing StatusInterleave Cache Program Operation ADQ0~ADQ15 Ongoing Status INT bitErase Command Sequence Block Erase Operation Timing125 Cold Reset Timing Warm Reset Timing CE, OE127 Hot Reset Timing Flex-MuxOneNANDADQi Nand Flash Core Reset Timing Data Protection Timing During Power DownFlex-MuxOneNAND Operation or Idle Nand Flash Core reset ADQiStatus RD Hi-Z RDY130 INT auto mode Write command into Command Register INT will automatically131 Methods of Determining Interrupt Status INT Type Mono INT Type DDPGeneral Operation DQ type 132Synchronous Mode Using the INT Pin Asynchronous Mode Using the INT PinINT Pin to a Host General Purpose I/O Polling the Interrupt Register Status Bit 134INT pol = ‘High’ Default Determining Rp Value DDP, QDP OnlyRpohm INT pol = ‘Low’ Vcc or VccqReady Vss KFN8GH6Q4M @ Vcc = 1.8V, Ta = 25C , CL = 30pFBoot Sequence Boot Loaders in Flex-MuxOneNANDBoot Sequence Boot Loaders in Flex-MuxOneNAND DescriptionNBL3 BL2BL1 NBL2Partition of Flex-MuxOneNAND MLC Partition +1 ~ n-1 BlocksLast Block Address First Block Address Data RegisterDDP and QDP Description DDPDual Die PackageQDPQuad Die Package 4G product KFM4GH6Q4M 8G product KFN8GH6Q4M141 16G product KFKAGH6Q4M 142

FLASH MEMORY

6.9 Load Operation Timing

See AC Characteristics Table 5.7 and Table 5.9

Load Command Sequence (last two cycles)

Read Data

Completed

Da+n

CLK

INT

RDY

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