Samsung KFKAGH6Q4M, KFN8GH6Q4M, KFM4GH6Q4M warranty LSB Page Recovery Read

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)	FLASH MEMORY

3.6.2 LSB Page Recovery Read

MLC NAND Flash cell has paired pages - LSB page and MSB page. LSB page has lower page address and MSB page has higher page address in paired pages. If power off occurs during MSB page program, the paired LSB page data can become corrupt. LSB page recovery read is a way to read LSB page though page data are corrupted. When uncorrectable error occurrs as a result of LSB page read after power up, issue LSB page recovery read. Its command is ‘0005h’. Flow chart below shows LSB page read sequence.

LSB Page Recovery read flow chart

Start
	DQ[10]=0?	NO	Write ‘DFS, FBA’ of Flash
			Add: F100h DQ=DFS*, FBA
Write ‘DFS, FBA’ of Flash
	YES
Add: F100h DQ=DFS*, FBA
	Read ECC Status Register1		Select DataRAM for DDP
Select DataRAM for DDP	Add: FF00h DQ=ER1[12:8],		Add: F101h DQ=DBS*
	ER0[4:0]
Add: F101h DQ=DBS*
			Write ‘FPA, FSA’ of Flash
	Read ECC Status Register2		Add: F107h DQ=FPA, FSA
Write ‘FPA, FSA’ of Flash	Add: FF01h DQ=ER3[12:8],
Add: F107h DQ=FPA, FSA	ER2[4:0]	Write ‘BSA, BSC’ of DataRAM
			Add: F200h DQ=0800h
Write ‘BSA1), BSC’ of DataRAM	Read ECC Status Register3
Add: F200h DQ=0800h	Add: FF02h DQ=ER5[12:8],		Write System Configuration
	ER4[4:0]
			Register
Write System Configuration	Read ECC Status Register4		Add: F221h DQ=ECC
Register
Add: F221h DQ=ECC	Add: FF03h DQ=ER7[12:8],
	ER6[4:0]		Write 0 to INT register
			Add: F241h DQ=0000h
Write 0 to INT register2)	Host reads data from
Add: F241h DQ=0000h	DataRAM	Write ‘LSB Page Recovery Read’
			Command
Write ‘Load’ Command	Read Completed		Add=F220h DQ=0005h
Add=F220h DQ=0000h
			Wait for INT register
Wait for INT register			low to high transition
			Add: F241h DQ[15]=INT
low to high transition
Add: F241h DQ[15]=INT		Read Controller status register
Read Controller status register			Add: F240h DQ[10]=Error
Add: F240h DQ[10]=Error		NO	YES
	Load Error
			DQ[10]=0?

Read ECC Status Register1

Add: FF00h DQ=ER1[12:8],

ER0[4:0]

Read ECC Status Register2

Add: FF01h DQ=ER3[12:8],

ER2[4:0]

Read ECC Status Register3

Add: FF02h DQ=ER5[12:8],

ER4[4:0]

Read ECC Status Register4

Add: FF03h DQ=ER7[12:8],

ER6[4:0]

Host reads data from

DataRAM

Read Completed

* DBS, DFS is for DDP

NOTE :

1)BSA must be 1000.

2)‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1

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