To install the Agilent E1439 | Agilent Technologies specs

Caution

Note

Note

Installing the Agilent E1439

To install the Agilent E1439

To install the Agilent E1439

To protect circuits from static discharge, observe anti-static techniques whenever handling the Agilent E1439 VXI ADC Module.

1.Set up your VXI mainframe. See the installation guide for your mainframe.

2.Select a slot in the VXI mainframe for the E1439 module.

The Agilent E1439D module’s local bus receives ECL-level data from the module immediately to its left and outputs ECL-level data to the module immediately to its right. Every module using the local bus is keyed to prevent two modules from fitting next to each other unless they are compatible. If you will be using the local bus, select adjacent slots immediately to the left of the data-receiving module. If the VXI bus is used, maximum data rates will be reduced but the module can be placed in any available slot.

3.Using a small screwdriver or similar tool, set the logical address configura- tion switch on the E1439. (See the illustration on the next page.) Each module in the system must have a unique logical address. The factory default setting is 1100 0000 (192).

For optimal phase noise performance in multi-module systems it is recommended that the first channel be an Agilent E1439C or D1. The Agilent E1439C does not support local bus or fiber optic transfers.

Multi-module systems may include multiple Agilent E1438s or Agilent E1439s but not a mixture of the two types of modules.

1As opposed to the older A or B models.

3

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Agilent Technologies manual To install the Agilent E1439

Contents

Agilent Technologies Part Number E1439-90005 Trademarks E1438 E1439 Agilent E1439 at a Glance Hardware What You Get With the Agilent E1439Software Documentation Other Documentation This BookPage Contents Contents Replacing Assemblies Contents Installing the Agilent E1439 To inspect the Agilent E1439 To inspect the Agilent E1439 To install the Agilent E1439 To install the Agilent E1439 Logical Address VXI Mainframe To clean fiber optic connectors To clean fiber optic connectors To transport the module To store the moduleTo store the module To transport the module Getting Started with the Agilent E1439 Getting Started and Introduction Getting Started and Introduction System Requirements System RequirementsSystem Requirements Microsoft Windows To install the Windows VXIplug&play drivers To install the Windows VXIplug&play driversUpdating firmware To use the Resource Manager To use the Resource Manager To use the program group Windows To use the program group Windows To use the VXIplug&play Soft Front Panel SFP To use the VXIplug&play Soft Front Panel SFP To use the example programs To use the example programs Info.exe Multchan32.exeInterrupt.exe Getting Started with the Agilent E1439 Using the Agilent E1439 Agilent E1439 overview Agilent E1439 overview Programming the Agilent E1439 Programming the Agilent E1439Windows framework Programming Measurement loop Measurement loop Measurement loop in multi-module systems Delay and phase in triggered measurements Delay and phase in triggered measurements Triggerdelayactual=0 or 0/16=0 output samples Using the Agilent E1439 Magnitude trigger and magdwell time Magnitude trigger and magdwell time Using the Agilent E1439 Frequency and filtering Frequency and filtering Using clock and sync Using clock and sync Managing multiple modules Sharing Reference and Sync signals in multi-module systemsManaging multiple modules Clock distribution Using the Agilent E1439 Managing multi-module systems Systems using front panel distribution Managing multi-mainframe systems Slot0 Controller Slave on Using an external sample clock Splitter External sample clock Synchronous digital filter changes Synchronizing changes in multi-module systemsSynchronous center frequency changes External sample synchronization in multi-module systems Trigger and phase in multi-module systems Sync the digital local oscillators Now you may take a measurement Issue an age1439measstart Transferring data Transferring data Fiber Optic Interface Fiber Optic Interface Data Frame Normal Data Fiber Frame Fiber FramesBOF Sync Without Data Fiber Frame EOE Sync with Data Fiber Frame Fiber Modes Fiber Interface SetupOff Copy Raw Generate Fiber Receiver Append Fiber Receiver Flow Control Copy No Copy2 Agilent E1439 Programmers Reference Introduction Introduction Functions listed by class Functions listed by classComponent Capability Subclass Function Name Component Capability Subclass Function Name Route Configure Route Configure LOW Level Age1439interruptrestore on Functions listed by functional group Functions listed by functional group Initializing and closing Debugging Agilent E1439 Programmers Reference Identification Trigger Synchronization controlling multiple modules Functions listed alphabetically Functions listed alphabetically Age1439driverdebuglevelget on page 97 −gets the debug level Agilent E1439 Programmers Reference Agilent E1439 Programmers Reference Agilent E1439 Programmers Reference Age1439adcclock AdcDivider AdcDividerPtr Age1439adcdividerAge1439adcdividerget Description Description Age1439attribget Board Age1439calgetDatestampPtr Age1439clockfsget Age1439clockfsViStatus age1439clockfsViSession id, ViReal64 fs ViStatus age1439clockfsgetViSession id, ViPReal64 fsPtr Age1439clockrecover ClockSetup Age1439clocksetupAge1439clocksetupget Phase locked to external reference Simple clock setups for stand-alone modulesInternal reference Front master, internal reference Front panel master-slave setups, one master per mainframe AGE1439FRNTREARMSTREXTREF Front slave, phase locked to master Rear master, phase locked to external reference Rear panel master-slave setups, one master per mainframeRear master, internal reference AGE1439REARSLAVEXTREF Front sync, external sample clock, wired-OR sync Send sync to slave Multiple mainframe setups Functions listed alphabetically Receive sync from master ClockSetupPtrExample Effect on Active Measurement ViStatus age1439closeViSession id Age1439closeAGE1439SUCCESS indicates that a function was successful Phase Age1439combosetupBlocksize Interpolate Age1439datamemsizeget Age1439datascaleget Age1439datasetup DataDelayPtr DataDelayData type BlocksizePtr ResolutionPtr ResolutionDataTypePtr Mode Port Xfers Sequence FilterBW Xfersize XfersizePtr Age1439dataxfersize DebugLevel DebugLevelPtr Age1439driverdebuglevel EpochGenerate Age1439epochsetup HeaderEnablePtr HeaderEnableEpochSizePtr HeaderValue Append Option/fiberMode Off 101 ErrorMessage Age1439errormessage ErrorCode ErrorMessage Age1439errorquery Age1439extsamplesync SyncEnable SyncEnablePtrAge1439extsamplesyncget 105 ViStatus age1439fiberclearViSession id Description Age1439fiberclearParameter ViStatus age1439fibererrorclearViSession id Age1439fibererrorclear Definition Numeric Description Value Age1439fibererrorget 109 LedRegPtr Age1439fiberLEDget Pio1 Pio2 Dir Nrdy Age1439fiberrcvsignalsget BofEnable Age1439fibersetup BofEnablePtr crcEnable CrcEnablePtr fiberMode FlowControlMode FibermodePtrTransferRate TransferRatePtr FiberSignalPtr Age1439fibersignalget VerifyPath Sec Age1439fiberverify ViStatus age1439fiberxmtBOFViSession id Age1439fiberxmtBOF Age1439fiberxmtsignals Age1439fiberxmtsignalsget Decimate Age1439filtersetupDecimatePtr Be set SigBwPtrInvalid parameter combinations 25 dB 15 dB ViStatus age1439filtersyncViSession id Description Age1439filtersyncComment 124 Comments Age1439frequencycenterraw 126 Age1439frequencycenterrawcompute Age1439frequencycenter sets the center frequency Age1439frequencysetupCenterFreq CenterFreqPtr Sync CmplxDCPtrSyncPtr 130 FpClock FpClockPtr Age1439frontpanelclockinputAge1439frontpanelclockinputget IdQuery Age1439init 133 ViStatus age1439inputautozeroViSession id Description Age1439inputautozero Age1439inputoffset ViStatus age1439inputoffsetsaveViSession id Age1439inputoffsetsave Age1439inputrangeauto Variable Range Index Age1439inputrangeconvertFull Scale Voltage Vp Full Scale DBm 140 AntiAlias Age1439inputsetup Range CouplingPtr SignalPtr SignalSignalPath SignalPathPtr 144 ViStatus age1439interruptrestoreViSession id Age1439interruptrestore Mask Age1439interruptsetup 147 Pipeline Age1439lbusmode LbusModePtr ViStatus age1439lbusresetViSession id, ViInt16 lbusReset Age1439lbusresetLbusReset LbusResetPtr Idle Sync Age1439meascontrol This function performs the following sequence 153 ViStatus age1439measinitViSession id Description Age1439measinit Age1439measstart Definition Age1439measstatusgetReadValid BlockReady Options Age1439optionsget ProductId Age1439productidget Checks for AGE1439STATUSREADBLOCK and AGE1439STATUS Age1439read SampleCount DataOverloadPtr Read or age1439read64 function is this 161 WordCount Age1439readraw Call age1439measstart Call age1439readraw 164 RefClock RefClockPtr Age1439referenceclockAge1439referenceclockget RefPrescaler RefPrescalerPtr Age1439referenceprescalerAge1439referenceprescalerget ViStatus age1439resetViSession id Description Age1439reset ViStatus age1439resethardViSession id Age1439resethard DriverRev InstrRev Age1439revisionquery Age1439selftest ErrorTestMessage TestResult Message 171 SerialNum Age1439serialnumberAge1439serialnumberget SmbClock SmbClockPtr Age1439smbclockoutputAge1439smbclockoutputget Age1439staterecall Age1439staterecall#include age1439.h ViStatus age1439staterecallViSession id Age1439statesave Age1439statesaveViStatus age1439statesaveViSession id Description Status Bit Definition Age1439statusget AGE1439STATUSREADVALID Status Bit Definition Description SyncClock SyncClockPtr Age1439syncclockAge1439syncclockget SyncDirection SyncDirectionPtr Age1439syncdirectionAge1439syncdirectionget SyncOutput SyncOutputPtr Age1439syncoutputAge1439syncoutputget ActualDelayPtr Age1439triggerdelayactualget ActualPhasePtr Age1439triggerphaseactualget Age1439triggersetup Post trigger Bit realPre-trigger GenTrigPtr Frequencysetup functionMagDwell MagDwellPtr TrigTypePtr VcxoState VcxoStatePtr Age1439vcxoAge1439vcxoget VxiClock VxiClockPtr Age1439vxiclockoutputAge1439vxiclockoutputget Age1439wait Equivalent numeric values for variables Equivalent numeric values for variablesVariable Name Numeric Value 191 192 193 194 195 196 197 Commands which halt active measurements Commands which halt active measurementsAge1439selftest age1439staterecall Error messages Error messagesParameter Description 200 Default values Default values Function VXIplug&play Syntax Quick Reference VXIplug&play Syntax Quick Reference Sage DacPtr 206 Module Description Front Panel Description Front Panel Description VXI backplane connections VXI backplane connections Trigger Lines Block diagram and description Block diagram and description Input Clock Generation DAC AC DC Anti-alias Filter Zoom and Decimation Filtering Sampling ADCMemory Controller and Sdram Memory Fiber Optic Interface Data Output Control Registers Trigger Detection 218 Replacing Assemblies Replaceable parts Replaceable partsOrdering Information Mfr. No Mfr. Name Location Code Numbers Assemblies Installing to avoid damage Part Number Replaceable parts Ref Des Agilent Part Qty DescriptionNumber To remove the top cover To remove the M1, M2 assemblies 226 Fiber frame that acts as a synchronizing event Agilent Technologies Sales OfficeFiber frame that contains the last 4 data bytes in an epoch Front panel data port 228 Index Index Raw data, scaling 231 VME VXI 234 Need Assistance? About this edition