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Agilent Technologies E1439 manual Replacing Assemblies

Models: E1439

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Replacing Assemblies

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Agilent Technologies E1439 manual Replacing Assemblies

Contents

Agilent Technologies Part Number E1439-90005 Trademarks E1438 E1439 Agilent E1439 at a GlanceHardware What You Get With the Agilent E1439Software DocumentationOther Documentation This BookPage Contents Contents Replacing Assemblies Contents Installing the Agilent E1439 To inspect the Agilent E1439 To inspect the Agilent E1439To install the Agilent E1439 To install the Agilent E1439Logical Address VXI Mainframe To clean fiber optic connectors To clean fiber optic connectorsTo transport the module To store the moduleTo store the module To transport the module Getting Started with the Agilent E1439 Getting Started and Introduction Getting Started and IntroductionSystem Requirements System RequirementsSystem Requirements Microsoft Windows To install the Windows VXIplug&play drivers To install the Windows VXIplug&play driversUpdating firmware To use the Resource Manager To use the Resource ManagerTo use the program group Windows To use the program group WindowsTo use the VXIplug&play Soft Front Panel SFP To use the VXIplug&play Soft Front Panel SFPTo use the example programs To use the example programsInfo.exe Multchan32.exeInterrupt.exe Getting Started with the Agilent E1439 Using the Agilent E1439 Agilent E1439 overview Agilent E1439 overviewProgramming the Agilent E1439 Programming the Agilent E1439Windows framework Programming Measurement loop Measurement loopMeasurement loop in multi-module systems Delay and phase in triggered measurements Delay and phase in triggered measurementsTriggerdelayactual=0 or 0/16=0 output samples Using the Agilent E1439 Magnitude trigger and magdwell time Magnitude trigger and magdwell timeUsing the Agilent E1439 Frequency and filtering Frequency and filteringUsing clock and sync Using clock and syncManaging multiple modules Sharing Reference and Sync signals in multi-module systemsManaging multiple modules Clock distributionUsing the Agilent E1439 Managing multi-module systems Systems using front panel distributionManaging multi-mainframe systems Slot0 ControllerSlave on Using an external sample clock Splitter External sample clock Synchronous digital filter changes Synchronizing changes in multi-module systemsSynchronous center frequency changes External sample synchronization in multi-module systems Trigger and phase in multi-module systemsSync the digital local oscillators Now you may take a measurement Issue an age1439measstartTransferring data Transferring dataFiber Optic Interface Fiber Optic InterfaceData Frame Normal Data Fiber Frame Fiber FramesBOF Sync Without Data Fiber Frame EOE Sync with Data Fiber FrameFiber Modes Fiber Interface SetupOff Copy Raw Generate Fiber Receiver Append Fiber Receiver Flow Control Copy No Copy2 Agilent E1439 Programmers Reference Introduction IntroductionFunctions listed by class Functions listed by classComponent Capability Subclass Function Name Component Capability Subclass Function Name Route Configure Route Configure LOW Level Age1439interruptrestore on Functions listed by functional group Functions listed by functional groupInitializing and closing Debugging Agilent E1439 Programmers Reference Identification Trigger Synchronization controlling multiple modules Functions listed alphabetically Functions listed alphabeticallyAge1439driverdebuglevelget on page 97 −gets the debug level Agilent E1439 Programmers Reference Agilent E1439 Programmers Reference Agilent E1439 Programmers Reference Age1439adcclock AdcDivider AdcDividerPtr Age1439adcdividerAge1439adcdividerget DescriptionDescription Age1439attribgetBoard Age1439calgetDatestampPtr Age1439clockfsget Age1439clockfsViStatus age1439clockfsViSession id, ViReal64 fs ViStatus age1439clockfsgetViSession id, ViPReal64 fsPtrAge1439clockrecover ClockSetup Age1439clocksetupAge1439clocksetupget Phase locked to external reference Simple clock setups for stand-alone modulesInternal reference Front master, internal reference Front panel master-slave setups, one master per mainframeAGE1439FRNTREARMSTREXTREF Front slave, phase locked to masterRear master, phase locked to external reference Rear panel master-slave setups, one master per mainframeRear master, internal reference AGE1439REARSLAVEXTREF Front sync, external sample clock, wired-OR syncSend sync to slave Multiple mainframe setupsFunctions listed alphabetically Receive sync from master ClockSetupPtrExample Effect on Active MeasurementViStatus age1439closeViSession id Age1439closeAGE1439SUCCESS indicates that a function was successful Phase Age1439combosetupBlocksize InterpolateAge1439datamemsizeget Age1439datascaleget Age1439datasetup DataDelayPtr DataDelayData type BlocksizePtrResolutionPtr ResolutionDataTypePtr ModePort Xfers Sequence FilterBW Xfersize XfersizePtr Age1439dataxfersizeDebugLevel DebugLevelPtr Age1439driverdebuglevelEpochGenerate Age1439epochsetupHeaderEnablePtr HeaderEnableEpochSizePtr HeaderValueAppend Option/fiberMode Off101 ErrorMessage Age1439errormessageErrorCode ErrorMessage Age1439errorqueryAge1439extsamplesync SyncEnable SyncEnablePtrAge1439extsamplesyncget 105 ViStatus age1439fiberclearViSession id Description Age1439fiberclearParameter ViStatus age1439fibererrorclearViSession id Age1439fibererrorclearDefinition Numeric Description Value Age1439fibererrorget109 LedRegPtr Age1439fiberLEDgetPio1 Pio2 Dir Nrdy Age1439fiberrcvsignalsgetBofEnable Age1439fibersetupBofEnablePtr crcEnable CrcEnablePtr fiberMode FlowControlMode FibermodePtrTransferRate TransferRatePtrFiberSignalPtr Age1439fibersignalgetVerifyPath Sec Age1439fiberverifyViStatus age1439fiberxmtBOFViSession id Age1439fiberxmtBOFAge1439fiberxmtsignals Age1439fiberxmtsignalsget Decimate Age1439filtersetupDecimatePtr Be set SigBwPtrInvalid parameter combinations 25 dB 15 dB ViStatus age1439filtersyncViSession id Description Age1439filtersyncComment 124 Comments Age1439frequencycenterraw126 Age1439frequencycenterrawcompute Age1439frequencycenter sets the center frequency Age1439frequencysetupCenterFreq CenterFreqPtrSync CmplxDCPtrSyncPtr 130 FpClock FpClockPtr Age1439frontpanelclockinputAge1439frontpanelclockinputget IdQuery Age1439init133 ViStatus age1439inputautozeroViSession id Description Age1439inputautozeroAge1439inputoffset ViStatus age1439inputoffsetsaveViSession id Age1439inputoffsetsaveAge1439inputrangeauto Variable Range Index Age1439inputrangeconvertFull Scale Voltage Vp Full Scale DBm 140 AntiAlias Age1439inputsetupRange CouplingPtrSignalPtr SignalSignalPath SignalPathPtr144 ViStatus age1439interruptrestoreViSession id Age1439interruptrestoreMask Age1439interruptsetup147 Pipeline Age1439lbusmodeLbusModePtr ViStatus age1439lbusresetViSession id, ViInt16 lbusReset Age1439lbusresetLbusReset LbusResetPtrIdle Sync Age1439meascontrolThis function performs the following sequence 153 ViStatus age1439measinitViSession id Description Age1439measinitAge1439measstart Definition Age1439measstatusgetReadValid BlockReadyOptions Age1439optionsgetProductId Age1439productidgetChecks for AGE1439STATUSREADBLOCK and AGE1439STATUS Age1439readSampleCount DataOverloadPtr Read or age1439read64 function is this161 WordCount Age1439readrawCall age1439measstart Call age1439readraw 164 RefClock RefClockPtr Age1439referenceclockAge1439referenceclockget RefPrescaler RefPrescalerPtr Age1439referenceprescalerAge1439referenceprescalerget ViStatus age1439resetViSession id Description Age1439resetViStatus age1439resethardViSession id Age1439resethardDriverRev InstrRev Age1439revisionqueryAge1439selftest ErrorTestMessage TestResult Message171 SerialNum Age1439serialnumberAge1439serialnumberget SmbClock SmbClockPtr Age1439smbclockoutputAge1439smbclockoutputget Age1439staterecall Age1439staterecall#include age1439.h ViStatus age1439staterecallViSession idAge1439statesave Age1439statesaveViStatus age1439statesaveViSession id Description Status Bit Definition Age1439statusgetAGE1439STATUSREADVALID Status Bit Definition DescriptionSyncClock SyncClockPtr Age1439syncclockAge1439syncclockget SyncDirection SyncDirectionPtr Age1439syncdirectionAge1439syncdirectionget SyncOutput SyncOutputPtr Age1439syncoutputAge1439syncoutputget ActualDelayPtr Age1439triggerdelayactualgetActualPhasePtr Age1439triggerphaseactualgetAge1439triggersetup Post trigger Bit realPre-trigger GenTrigPtr Frequencysetup functionMagDwell MagDwellPtrTrigTypePtr VcxoState VcxoStatePtr Age1439vcxoAge1439vcxoget VxiClock VxiClockPtr Age1439vxiclockoutputAge1439vxiclockoutputget Age1439wait Equivalent numeric values for variables Equivalent numeric values for variablesVariable Name Numeric Value 191 192 193 194 195 196 197 Commands which halt active measurements Commands which halt active measurementsAge1439selftest age1439staterecall Error messages Error messagesParameter Description 200 Default values Default valuesFunction VXIplug&play Syntax Quick Reference VXIplug&play Syntax Quick ReferenceSage DacPtr 206 Module Description Front Panel Description Front Panel DescriptionVXI backplane connections VXI backplane connectionsTrigger Lines Block diagram and description Block diagram and descriptionInput Clock Generation DAC AC DCAnti-alias Filter Zoom and Decimation Filtering Sampling ADCMemory Controller and Sdram Memory Fiber Optic Interface Data OutputControl Registers Trigger Detection218 Replacing Assemblies Replaceable parts Replaceable partsOrdering Information Mfr. No Mfr. Name Location Code NumbersAssemblies Installing to avoid damagePart Number Replaceable parts Ref Des Agilent Part Qty DescriptionNumber To remove the top cover To remove the M1, M2 assemblies 226 Fiber frame that acts as a synchronizing event Agilent Technologies Sales OfficeFiber frame that contains the last 4 data bytes in an epoch Front panel data port228 Index Index Raw data, scaling 231 VME VXI 234 Need Assistance? About this edition