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Agilent Technologies E1439 manual

Models: E1439

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Agilent Technologies E1439 manual

Contents

Agilent Technologies Part Number E1439-90005 Trademarks Agilent E1439 at a Glance E1438 E1439Software What You Get With the Agilent E1439Hardware DocumentationThis Book Other DocumentationPage Contents Contents Replacing Assemblies Contents Installing the Agilent E1439 To inspect the Agilent E1439 To inspect the Agilent E1439To install the Agilent E1439 To install the Agilent E1439Logical Address VXI Mainframe To clean fiber optic connectors To clean fiber optic connectorsTo store the module To transport the moduleTo store the module To transport the module Getting Started with the Agilent E1439 Getting Started and Introduction Getting Started and IntroductionSystem Requirements System RequirementsSystem Requirements Microsoft Windows To install the Windows VXIplug&play drivers To install the Windows VXIplug&play driversUpdating firmware To use the Resource Manager To use the Resource ManagerTo use the program group Windows To use the program group WindowsTo use the VXIplug&play Soft Front Panel SFP To use the VXIplug&play Soft Front Panel SFPTo use the example programs To use the example programsMultchan32.exe Info.exeInterrupt.exe Getting Started with the Agilent E1439 Using the Agilent E1439 Agilent E1439 overview Agilent E1439 overviewProgramming the Agilent E1439 Programming the Agilent E1439Windows framework Programming Measurement loop Measurement loopMeasurement loop in multi-module systems Delay and phase in triggered measurements Delay and phase in triggered measurementsTriggerdelayactual=0 or 0/16=0 output samples Using the Agilent E1439 Magnitude trigger and magdwell time Magnitude trigger and magdwell timeUsing the Agilent E1439 Frequency and filtering Frequency and filteringUsing clock and sync Using clock and syncManaging multiple modules Sharing Reference and Sync signals in multi-module systemsManaging multiple modules Clock distributionUsing the Agilent E1439 Systems using front panel distribution Managing multi-module systemsSlot0 Controller Managing multi-mainframe systemsSlave on Using an external sample clock Splitter External sample clock Synchronizing changes in multi-module systems Synchronous digital filter changesSynchronous center frequency changes Trigger and phase in multi-module systems External sample synchronization in multi-module systemsNow you may take a measurement Issue an age1439measstart Sync the digital local oscillatorsTransferring data Transferring dataFiber Optic Interface Fiber Optic InterfaceBOF Sync Without Data Fiber Frame Fiber FramesData Frame Normal Data Fiber Frame EOE Sync with Data Fiber FrameFiber Interface Setup Fiber ModesOff Copy Raw Generate Fiber Receiver Append Fiber Receiver Flow Control Copy No Copy2 Agilent E1439 Programmers Reference Introduction IntroductionFunctions listed by class Functions listed by classComponent Capability Subclass Function Name Component Capability Subclass Function Name Route Configure Route Configure LOW Level Age1439interruptrestore on Functions listed by functional group Functions listed by functional groupInitializing and closing Debugging Agilent E1439 Programmers Reference Identification Trigger Synchronization controlling multiple modules Functions listed alphabetically Functions listed alphabeticallyAge1439driverdebuglevelget on page 97 −gets the debug level Agilent E1439 Programmers Reference Agilent E1439 Programmers Reference Agilent E1439 Programmers Reference Age1439adcclock Age1439adcdividerget Age1439adcdividerAdcDivider AdcDividerPtr DescriptionAge1439attribget DescriptionAge1439calget BoardDatestampPtr ViStatus age1439clockfsViSession id, ViReal64 fs Age1439clockfsAge1439clockfsget ViStatus age1439clockfsgetViSession id, ViPReal64 fsPtrAge1439clockrecover Age1439clocksetup ClockSetupAge1439clocksetupget Simple clock setups for stand-alone modules Phase locked to external referenceInternal reference Front panel master-slave setups, one master per mainframe Front master, internal referenceFront slave, phase locked to master AGE1439FRNTREARMSTREXTREFRear panel master-slave setups, one master per mainframe Rear master, phase locked to external referenceRear master, internal reference Front sync, external sample clock, wired-OR sync AGE1439REARSLAVEXTREFMultiple mainframe setups Send sync to slaveExample ClockSetupPtrFunctions listed alphabetically Receive sync from master Effect on Active MeasurementAge1439close ViStatus age1439closeViSession idAGE1439SUCCESS indicates that a function was successful Blocksize Age1439combosetupPhase InterpolateAge1439datamemsizeget Age1439datascaleget Age1439datasetup Data type DataDelayDataDelayPtr BlocksizePtrDataTypePtr ResolutionResolutionPtr ModePort Xfers Sequence FilterBW Age1439dataxfersize Xfersize XfersizePtrAge1439driverdebuglevel DebugLevel DebugLevelPtrAge1439epochsetup EpochGenerateEpochSizePtr HeaderEnableHeaderEnablePtr HeaderValueOption/fiberMode Off Append101 Age1439errormessage ErrorMessageAge1439errorquery ErrorCode ErrorMessageSyncEnable SyncEnablePtr Age1439extsamplesyncAge1439extsamplesyncget 105 Age1439fiberclear ViStatus age1439fiberclearViSession id DescriptionParameter Age1439fibererrorclear ViStatus age1439fibererrorclearViSession idAge1439fibererrorget Definition Numeric Description Value109 Age1439fiberLEDget LedRegPtrAge1439fiberrcvsignalsget Pio1 Pio2 Dir NrdyAge1439fibersetup BofEnableBofEnablePtr crcEnable CrcEnablePtr fiberMode TransferRate FibermodePtrFlowControlMode TransferRatePtrAge1439fibersignalget FiberSignalPtrAge1439fiberverify VerifyPath SecAge1439fiberxmtBOF ViStatus age1439fiberxmtBOFViSession idAge1439fiberxmtsignals Age1439fiberxmtsignalsget Age1439filtersetup DecimateDecimatePtr SigBwPtr Be setInvalid parameter combinations 25 dB 15 dB Age1439filtersync ViStatus age1439filtersyncViSession id DescriptionComment 124 Age1439frequencycenterraw Comments126 Age1439frequencycenterrawcompute CenterFreq Age1439frequencysetupAge1439frequencycenter sets the center frequency CenterFreqPtrCmplxDCPtr SyncSyncPtr 130 Age1439frontpanelclockinput FpClock FpClockPtrAge1439frontpanelclockinputget Age1439init IdQuery133 Age1439inputautozero ViStatus age1439inputautozeroViSession id DescriptionAge1439inputoffset Age1439inputoffsetsave ViStatus age1439inputoffsetsaveViSession idAge1439inputrangeauto Age1439inputrangeconvert Variable Range IndexFull Scale Voltage Vp Full Scale DBm 140 Age1439inputsetup AntiAliasCouplingPtr RangeSignalPath SignalSignalPtr SignalPathPtr144 Age1439interruptrestore ViStatus age1439interruptrestoreViSession idAge1439interruptsetup Mask147 Age1439lbusmode PipelineLbusModePtr LbusReset Age1439lbusresetViStatus age1439lbusresetViSession id, ViInt16 lbusReset LbusResetPtrAge1439meascontrol Idle SyncThis function performs the following sequence 153 Age1439measinit ViStatus age1439measinitViSession id DescriptionAge1439measstart ReadValid Age1439measstatusgetDefinition BlockReadyAge1439optionsget OptionsAge1439productidget ProductIdAge1439read Checks for AGE1439STATUSREADBLOCK and AGE1439STATUSOverloadPtr DataSampleCount Read or age1439read64 function is this161 Age1439readraw WordCountCall age1439measstart Call age1439readraw 164 Age1439referenceclock RefClock RefClockPtrAge1439referenceclockget Age1439referenceprescaler RefPrescaler RefPrescalerPtrAge1439referenceprescalerget Age1439reset ViStatus age1439resetViSession id DescriptionAge1439resethard ViStatus age1439resethardViSession idAge1439revisionquery DriverRev InstrRevTestMessage TestResult ErrorAge1439selftest Message171 Age1439serialnumber SerialNumAge1439serialnumberget Age1439smbclockoutput SmbClock SmbClockPtrAge1439smbclockoutputget #include age1439.h Age1439staterecallAge1439staterecall ViStatus age1439staterecallViSession idAge1439statesave Age1439statesaveViStatus age1439statesaveViSession id Description Age1439statusget Status Bit DefinitionStatus Bit Definition Description AGE1439STATUSREADVALIDAge1439syncclock SyncClock SyncClockPtrAge1439syncclockget Age1439syncdirection SyncDirection SyncDirectionPtrAge1439syncdirectionget Age1439syncoutput SyncOutput SyncOutputPtrAge1439syncoutputget Age1439triggerdelayactualget ActualDelayPtrAge1439triggerphaseactualget ActualPhasePtrAge1439triggersetup Bit real Post triggerPre-trigger MagDwell Frequencysetup functionGenTrigPtr MagDwellPtrTrigTypePtr Age1439vcxo VcxoState VcxoStatePtrAge1439vcxoget Age1439vxiclockoutput VxiClock VxiClockPtrAge1439vxiclockoutputget Age1439wait Equivalent numeric values for variables Equivalent numeric values for variablesVariable Name Numeric Value 191 192 193 194 195 196 197 Commands which halt active measurements Commands which halt active measurementsAge1439selftest age1439staterecall Error messages Error messagesParameter Description 200 Default values Default valuesFunction VXIplug&play Syntax Quick Reference VXIplug&play Syntax Quick ReferenceSage DacPtr 206 Module Description Front Panel Description Front Panel DescriptionVXI backplane connections VXI backplane connectionsTrigger Lines Block diagram and description Block diagram and descriptionInput DAC AC DC Clock GenerationAnti-alias Filter Sampling ADC Zoom and Decimation FilteringMemory Controller and Sdram Memory Data Output Fiber Optic InterfaceTrigger Detection Control Registers218 Replacing Assemblies Replaceable parts Replaceable partsOrdering Information Code Numbers Mfr. No Mfr. Name LocationInstalling to avoid damage AssembliesReplaceable parts Ref Des Agilent Part Qty Description Part NumberNumber To remove the top cover To remove the M1, M2 assemblies 226 Fiber frame that contains the last 4 data bytes in an epoch Agilent Technologies Sales OfficeFiber frame that acts as a synchronizing event Front panel data port228 Index Index Raw data, scaling 231 VME VXI 234 Need Assistance? About this edition