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Agilent Technologies E1439 manual 234

Models: E1439

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Agilent Technologies E1439 manual 234

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Agilent Technologies Part Number E1439-90005 Trademarks Agilent E1439 at a Glance E1438 E1439What You Get With the Agilent E1439 HardwareSoftware DocumentationThis Book Other DocumentationPage Contents Contents Replacing Assemblies Contents Installing the Agilent E1439 To inspect the Agilent E1439 To inspect the Agilent E1439To install the Agilent E1439 To install the Agilent E1439Logical Address VXI Mainframe To clean fiber optic connectors To clean fiber optic connectorsTo transport the module To store the moduleTo store the module To transport the module Getting Started with the Agilent E1439 Getting Started and Introduction Getting Started and IntroductionSystem Requirements System RequirementsSystem Requirements Microsoft Windows To install the Windows VXIplug&play drivers To install the Windows VXIplug&play driversUpdating firmware To use the Resource Manager To use the Resource ManagerTo use the program group Windows To use the program group WindowsTo use the VXIplug&play Soft Front Panel SFP To use the VXIplug&play Soft Front Panel SFPTo use the example programs To use the example programsInfo.exe Multchan32.exeInterrupt.exe Getting Started with the Agilent E1439 Using the Agilent E1439 Agilent E1439 overview Agilent E1439 overviewProgramming the Agilent E1439 Programming the Agilent E1439Windows framework Programming Measurement loop Measurement loopMeasurement loop in multi-module systems Delay and phase in triggered measurements Delay and phase in triggered measurementsTriggerdelayactual=0 or 0/16=0 output samples Using the Agilent E1439 Magnitude trigger and magdwell time Magnitude trigger and magdwell timeUsing the Agilent E1439 Frequency and filtering Frequency and filteringUsing clock and sync Using clock and syncSharing Reference and Sync signals in multi-module systems Managing multiple modulesManaging multiple modules Clock distributionUsing the Agilent E1439 Systems using front panel distribution Managing multi-module systemsSlot0 Controller Managing multi-mainframe systemsSlave on Using an external sample clock Splitter External sample clock Synchronous digital filter changes Synchronizing changes in multi-module systemsSynchronous center frequency changes Trigger and phase in multi-module systems External sample synchronization in multi-module systemsNow you may take a measurement Issue an age1439measstart Sync the digital local oscillatorsTransferring data Transferring dataFiber Optic Interface Fiber Optic InterfaceFiber Frames Data Frame Normal Data Fiber FrameBOF Sync Without Data Fiber Frame EOE Sync with Data Fiber FrameFiber Modes Fiber Interface SetupOff Copy Raw Generate Fiber Receiver Append Fiber Receiver Flow Control Copy No Copy2 Agilent E1439 Programmers Reference Introduction IntroductionFunctions listed by class Functions listed by classComponent Capability Subclass Function Name Component Capability Subclass Function Name Route Configure Route Configure LOW Level Age1439interruptrestore on Functions listed by functional group Functions listed by functional groupInitializing and closing Debugging Agilent E1439 Programmers Reference Identification Trigger Synchronization controlling multiple modules Functions listed alphabetically Functions listed alphabeticallyAge1439driverdebuglevelget on page 97 −gets the debug level Agilent E1439 Programmers Reference Agilent E1439 Programmers Reference Agilent E1439 Programmers Reference Age1439adcclock Age1439adcdivider AdcDivider AdcDividerPtrAge1439adcdividerget DescriptionAge1439attribget DescriptionBoard Age1439calgetDatestampPtr Age1439clockfs Age1439clockfsgetViStatus age1439clockfsViSession id, ViReal64 fs ViStatus age1439clockfsgetViSession id, ViPReal64 fsPtrAge1439clockrecover ClockSetup Age1439clocksetupAge1439clocksetupget Phase locked to external reference Simple clock setups for stand-alone modulesInternal reference Front panel master-slave setups, one master per mainframe Front master, internal referenceFront slave, phase locked to master AGE1439FRNTREARMSTREXTREFRear master, phase locked to external reference Rear panel master-slave setups, one master per mainframeRear master, internal reference Front sync, external sample clock, wired-OR sync AGE1439REARSLAVEXTREFMultiple mainframe setups Send sync to slaveClockSetupPtr Functions listed alphabetically Receive sync from masterExample Effect on Active MeasurementViStatus age1439closeViSession id Age1439closeAGE1439SUCCESS indicates that a function was successful Age1439combosetup PhaseBlocksize InterpolateAge1439datamemsizeget Age1439datascaleget Age1439datasetup DataDelay DataDelayPtrData type BlocksizePtrResolution ResolutionPtrDataTypePtr ModePort Xfers Sequence FilterBW Age1439dataxfersize Xfersize XfersizePtrAge1439driverdebuglevel DebugLevel DebugLevelPtrAge1439epochsetup EpochGenerateHeaderEnable HeaderEnablePtrEpochSizePtr HeaderValueOption/fiberMode Off Append101 Age1439errormessage ErrorMessageAge1439errorquery ErrorCode ErrorMessageAge1439extsamplesync SyncEnable SyncEnablePtrAge1439extsamplesyncget 105 ViStatus age1439fiberclearViSession id Description Age1439fiberclearParameter Age1439fibererrorclear ViStatus age1439fibererrorclearViSession idAge1439fibererrorget Definition Numeric Description Value109 Age1439fiberLEDget LedRegPtrAge1439fiberrcvsignalsget Pio1 Pio2 Dir NrdyAge1439fibersetup BofEnableBofEnablePtr crcEnable CrcEnablePtr fiberMode FibermodePtr FlowControlModeTransferRate TransferRatePtrAge1439fibersignalget FiberSignalPtrAge1439fiberverify VerifyPath SecAge1439fiberxmtBOF ViStatus age1439fiberxmtBOFViSession idAge1439fiberxmtsignals Age1439fiberxmtsignalsget Decimate Age1439filtersetupDecimatePtr Be set SigBwPtrInvalid parameter combinations 25 dB 15 dB ViStatus age1439filtersyncViSession id Description Age1439filtersyncComment 124 Age1439frequencycenterraw Comments126 Age1439frequencycenterrawcompute Age1439frequencysetup Age1439frequencycenter sets the center frequencyCenterFreq CenterFreqPtrSync CmplxDCPtrSyncPtr 130 FpClock FpClockPtr Age1439frontpanelclockinputAge1439frontpanelclockinputget Age1439init IdQuery133 Age1439inputautozero ViStatus age1439inputautozeroViSession id DescriptionAge1439inputoffset Age1439inputoffsetsave ViStatus age1439inputoffsetsaveViSession idAge1439inputrangeauto Variable Range Index Age1439inputrangeconvertFull Scale Voltage Vp Full Scale DBm 140 Age1439inputsetup AntiAliasCouplingPtr RangeSignal SignalPtrSignalPath SignalPathPtr144 Age1439interruptrestore ViStatus age1439interruptrestoreViSession idAge1439interruptsetup Mask147 Age1439lbusmode PipelineLbusModePtr Age1439lbusreset ViStatus age1439lbusresetViSession id, ViInt16 lbusResetLbusReset LbusResetPtrAge1439meascontrol Idle SyncThis function performs the following sequence 153 Age1439measinit ViStatus age1439measinitViSession id DescriptionAge1439measstart Age1439measstatusget DefinitionReadValid BlockReadyAge1439optionsget OptionsAge1439productidget ProductIdAge1439read Checks for AGE1439STATUSREADBLOCK and AGE1439STATUSData SampleCountOverloadPtr Read or age1439read64 function is this161 Age1439readraw WordCountCall age1439measstart Call age1439readraw 164 RefClock RefClockPtr Age1439referenceclockAge1439referenceclockget RefPrescaler RefPrescalerPtr Age1439referenceprescalerAge1439referenceprescalerget Age1439reset ViStatus age1439resetViSession id DescriptionAge1439resethard ViStatus age1439resethardViSession idAge1439revisionquery DriverRev InstrRevError Age1439selftestTestMessage TestResult Message171 SerialNum Age1439serialnumberAge1439serialnumberget SmbClock SmbClockPtr Age1439smbclockoutputAge1439smbclockoutputget Age1439staterecall Age1439staterecall#include age1439.h ViStatus age1439staterecallViSession idAge1439statesave Age1439statesaveViStatus age1439statesaveViSession id Description Age1439statusget Status Bit DefinitionStatus Bit Definition Description AGE1439STATUSREADVALIDSyncClock SyncClockPtr Age1439syncclockAge1439syncclockget SyncDirection SyncDirectionPtr Age1439syncdirectionAge1439syncdirectionget SyncOutput SyncOutputPtr Age1439syncoutputAge1439syncoutputget Age1439triggerdelayactualget ActualDelayPtrAge1439triggerphaseactualget ActualPhasePtrAge1439triggersetup Post trigger Bit realPre-trigger Frequencysetup function GenTrigPtrMagDwell MagDwellPtrTrigTypePtr VcxoState VcxoStatePtr Age1439vcxoAge1439vcxoget VxiClock VxiClockPtr Age1439vxiclockoutputAge1439vxiclockoutputget Age1439wait Equivalent numeric values for variables Equivalent numeric values for variablesVariable Name Numeric Value 191 192 193 194 195 196 197 Commands which halt active measurements Commands which halt active measurementsAge1439selftest age1439staterecall Error messages Error messagesParameter Description 200 Default values Default valuesFunction VXIplug&play Syntax Quick Reference VXIplug&play Syntax Quick ReferenceSage DacPtr 206 Module Description Front Panel Description Front Panel DescriptionVXI backplane connections VXI backplane connectionsTrigger Lines Block diagram and description Block diagram and descriptionInput DAC AC DC Clock GenerationAnti-alias Filter Zoom and Decimation Filtering Sampling ADCMemory Controller and Sdram Memory Data Output Fiber Optic InterfaceTrigger Detection Control Registers218 Replacing Assemblies Replaceable parts Replaceable partsOrdering Information Code Numbers Mfr. No Mfr. Name LocationInstalling to avoid damage AssembliesPart Number Replaceable parts Ref Des Agilent Part Qty DescriptionNumber To remove the top cover To remove the M1, M2 assemblies 226 Agilent Technologies Sales Office Fiber frame that acts as a synchronizing eventFiber frame that contains the last 4 data bytes in an epoch Front panel data port228 Index Index Raw data, scaling 231 VME VXI 234 Need Assistance? About this edition