To transport the module | Agilent Technologies E1439 specs

Installing the Agilent E1439

To transport the module

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Agilent Technologies E1439 manual To transport the module

Contents

Agilent Technologies Part Number E1439-90005 Trademarks Agilent E1439 at a Glance E1438 E1439 Software What You Get With the Agilent E1439Hardware Documentation This Book Other DocumentationPage Contents Contents Replacing Assemblies Contents Installing the Agilent E1439 To inspect the Agilent E1439 To inspect the Agilent E1439 To install the Agilent E1439 To install the Agilent E1439 Logical Address VXI Mainframe To clean fiber optic connectors To clean fiber optic connectors To store the module To transport the moduleTo store the module To transport the module Getting Started with the Agilent E1439 Getting Started and Introduction Getting Started and Introduction System Requirements System RequirementsSystem Requirements Microsoft Windows To install the Windows VXIplug&play drivers To install the Windows VXIplug&play driversUpdating firmware To use the Resource Manager To use the Resource Manager To use the program group Windows To use the program group Windows To use the VXIplug&play Soft Front Panel SFP To use the VXIplug&play Soft Front Panel SFP To use the example programs To use the example programs Multchan32.exe Info.exeInterrupt.exe Getting Started with the Agilent E1439 Using the Agilent E1439 Agilent E1439 overview Agilent E1439 overview Programming the Agilent E1439 Programming the Agilent E1439Windows framework Programming Measurement loop Measurement loop Measurement loop in multi-module systems Delay and phase in triggered measurements Delay and phase in triggered measurements Triggerdelayactual=0 or 0/16=0 output samples Using the Agilent E1439 Magnitude trigger and magdwell time Magnitude trigger and magdwell time Using the Agilent E1439 Frequency and filtering Frequency and filtering Using clock and sync Using clock and sync Managing multiple modules Sharing Reference and Sync signals in multi-module systemsManaging multiple modules Clock distribution Using the Agilent E1439 Systems using front panel distribution Managing multi-module systems Slot0 Controller Managing multi-mainframe systems Slave on Using an external sample clock Splitter External sample clock Synchronizing changes in multi-module systems Synchronous digital filter changesSynchronous center frequency changes Trigger and phase in multi-module systems External sample synchronization in multi-module systems Now you may take a measurement Issue an age1439measstart Sync the digital local oscillators Transferring data Transferring data Fiber Optic Interface Fiber Optic Interface BOF Sync Without Data Fiber Frame Fiber FramesData Frame Normal Data Fiber Frame EOE Sync with Data Fiber Frame Fiber Interface Setup Fiber ModesOff Copy Raw Generate Fiber Receiver Append Fiber Receiver Flow Control Copy No Copy2 Agilent E1439 Programmers Reference Introduction Introduction Functions listed by class Functions listed by classComponent Capability Subclass Function Name Component Capability Subclass Function Name Route Configure Route Configure LOW Level Age1439interruptrestore on Functions listed by functional group Functions listed by functional group Initializing and closing Debugging Agilent E1439 Programmers Reference Identification Trigger Synchronization controlling multiple modules Functions listed alphabetically Functions listed alphabetically Age1439driverdebuglevelget on page 97 −gets the debug level Agilent E1439 Programmers Reference Agilent E1439 Programmers Reference Agilent E1439 Programmers Reference Age1439adcclock Age1439adcdividerget Age1439adcdividerAdcDivider AdcDividerPtr Description Age1439attribget Description Age1439calget BoardDatestampPtr ViStatus age1439clockfsViSession id, ViReal64 fs Age1439clockfsAge1439clockfsget ViStatus age1439clockfsgetViSession id, ViPReal64 fsPtr Age1439clockrecover Age1439clocksetup ClockSetupAge1439clocksetupget Simple clock setups for stand-alone modules Phase locked to external referenceInternal reference Front panel master-slave setups, one master per mainframe Front master, internal reference Front slave, phase locked to master AGE1439FRNTREARMSTREXTREF Rear panel master-slave setups, one master per mainframe Rear master, phase locked to external referenceRear master, internal reference Front sync, external sample clock, wired-OR sync AGE1439REARSLAVEXTREF Multiple mainframe setups Send sync to slave Example ClockSetupPtrFunctions listed alphabetically Receive sync from master Effect on Active Measurement Age1439close ViStatus age1439closeViSession idAGE1439SUCCESS indicates that a function was successful Blocksize Age1439combosetupPhase Interpolate Age1439datamemsizeget Age1439datascaleget Age1439datasetup Data type DataDelayDataDelayPtr BlocksizePtr DataTypePtr ResolutionResolutionPtr Mode Port Xfers Sequence FilterBW Age1439dataxfersize Xfersize XfersizePtr Age1439driverdebuglevel DebugLevel DebugLevelPtr Age1439epochsetup EpochGenerate EpochSizePtr HeaderEnableHeaderEnablePtr HeaderValue Option/fiberMode Off Append 101 Age1439errormessage ErrorMessage Age1439errorquery ErrorCode ErrorMessage SyncEnable SyncEnablePtr Age1439extsamplesyncAge1439extsamplesyncget 105 Age1439fiberclear ViStatus age1439fiberclearViSession id DescriptionParameter Age1439fibererrorclear ViStatus age1439fibererrorclearViSession id Age1439fibererrorget Definition Numeric Description Value 109 Age1439fiberLEDget LedRegPtr Age1439fiberrcvsignalsget Pio1 Pio2 Dir Nrdy Age1439fibersetup BofEnable BofEnablePtr crcEnable CrcEnablePtr fiberMode TransferRate FibermodePtrFlowControlMode TransferRatePtr Age1439fibersignalget FiberSignalPtr Age1439fiberverify VerifyPath Sec Age1439fiberxmtBOF ViStatus age1439fiberxmtBOFViSession id Age1439fiberxmtsignals Age1439fiberxmtsignalsget Age1439filtersetup DecimateDecimatePtr SigBwPtr Be setInvalid parameter combinations 25 dB 15 dB Age1439filtersync ViStatus age1439filtersyncViSession id DescriptionComment 124 Age1439frequencycenterraw Comments 126 Age1439frequencycenterrawcompute CenterFreq Age1439frequencysetupAge1439frequencycenter sets the center frequency CenterFreqPtr CmplxDCPtr SyncSyncPtr 130 Age1439frontpanelclockinput FpClock FpClockPtrAge1439frontpanelclockinputget Age1439init IdQuery 133 Age1439inputautozero ViStatus age1439inputautozeroViSession id Description Age1439inputoffset Age1439inputoffsetsave ViStatus age1439inputoffsetsaveViSession id Age1439inputrangeauto Age1439inputrangeconvert Variable Range IndexFull Scale Voltage Vp Full Scale DBm 140 Age1439inputsetup AntiAlias CouplingPtr Range SignalPath SignalSignalPtr SignalPathPtr 144 Age1439interruptrestore ViStatus age1439interruptrestoreViSession id Age1439interruptsetup Mask 147 Age1439lbusmode Pipeline LbusModePtr LbusReset Age1439lbusresetViStatus age1439lbusresetViSession id, ViInt16 lbusReset LbusResetPtr Age1439meascontrol Idle Sync This function performs the following sequence 153 Age1439measinit ViStatus age1439measinitViSession id Description Age1439measstart ReadValid Age1439measstatusgetDefinition BlockReady Age1439optionsget Options Age1439productidget ProductId Age1439read Checks for AGE1439STATUSREADBLOCK and AGE1439STATUS OverloadPtr DataSampleCount Read or age1439read64 function is this 161 Age1439readraw WordCount Call age1439measstart Call age1439readraw 164 Age1439referenceclock RefClock RefClockPtrAge1439referenceclockget Age1439referenceprescaler RefPrescaler RefPrescalerPtrAge1439referenceprescalerget Age1439reset ViStatus age1439resetViSession id Description Age1439resethard ViStatus age1439resethardViSession id Age1439revisionquery DriverRev InstrRev TestMessage TestResult ErrorAge1439selftest Message 171 Age1439serialnumber SerialNumAge1439serialnumberget Age1439smbclockoutput SmbClock SmbClockPtrAge1439smbclockoutputget #include age1439.h Age1439staterecallAge1439staterecall ViStatus age1439staterecallViSession id Age1439statesave Age1439statesaveViStatus age1439statesaveViSession id Description Age1439statusget Status Bit Definition Status Bit Definition Description AGE1439STATUSREADVALID Age1439syncclock SyncClock SyncClockPtrAge1439syncclockget Age1439syncdirection SyncDirection SyncDirectionPtrAge1439syncdirectionget Age1439syncoutput SyncOutput SyncOutputPtrAge1439syncoutputget Age1439triggerdelayactualget ActualDelayPtr Age1439triggerphaseactualget ActualPhasePtr Age1439triggersetup Bit real Post triggerPre-trigger MagDwell Frequencysetup functionGenTrigPtr MagDwellPtr TrigTypePtr Age1439vcxo VcxoState VcxoStatePtrAge1439vcxoget Age1439vxiclockoutput VxiClock VxiClockPtrAge1439vxiclockoutputget Age1439wait Equivalent numeric values for variables Equivalent numeric values for variablesVariable Name Numeric Value 191 192 193 194 195 196 197 Commands which halt active measurements Commands which halt active measurementsAge1439selftest age1439staterecall Error messages Error messagesParameter Description 200 Default values Default values Function VXIplug&play Syntax Quick Reference VXIplug&play Syntax Quick Reference Sage DacPtr 206 Module Description Front Panel Description Front Panel Description VXI backplane connections VXI backplane connections Trigger Lines Block diagram and description Block diagram and description Input DAC AC DC Clock Generation Anti-alias Filter Sampling ADC Zoom and Decimation FilteringMemory Controller and Sdram Memory Data Output Fiber Optic Interface Trigger Detection Control Registers 218 Replacing Assemblies Replaceable parts Replaceable partsOrdering Information Code Numbers Mfr. No Mfr. Name Location Installing to avoid damage Assemblies Replaceable parts Ref Des Agilent Part Qty Description Part NumberNumber To remove the top cover To remove the M1, M2 assemblies 226 Fiber frame that contains the last 4 data bytes in an epoch Agilent Technologies Sales OfficeFiber frame that acts as a synchronizing event Front panel data port 228 Index Index Raw data, scaling 231 VME VXI 234 Need Assistance? About this edition