Agilent Technologies E1439 manual Measurement loop

Using the Agilent E1439

The measurement loop

The measurement loop

The measurement loop progresses through four states. The transition from one state to the next is tied to the transition of the Sync signal. The effect of the Sync signal is summarized in the following diagram representing the four possible states of an Agilent E1439 module.

No data collected		Assert			New data collected
Old data available	IDLE		ARM		Old data cleared
Release				Release
(Block Mode)

Data collected and output	Measure		Trigger	Data collected
		Assert		Pre-trigger data cleared

In the Idle state, the E1439 places no new data into the FIFO output buffer memory although previously measured data is retained in the buffer memory and is available for output via the VME (and also local bus, or fiber optic transmitter port on the E1439D). The module stays in the Idle state until the Sync line is asserted.

Upon entering the Arm state the E1439 clears old data. It remains in the Arm state until the Sync signal is released. If an E1439 is programmed with a pre-trigger delay, it collects enough data samples to satisfy this pre-trigger delay, and then releases the Sync line. If no pre-trigger delay has been programmed, the module releases the Sync line immediately. When all E1439s in a system have released the Sync line, the module moves to the Trigger state.

Upon entering the Trigger state, an E1439 that is programmed with a pre-trigger delay continues collecting data into the FIFO, discarding any data prior to the pre-trigger delay. An E1439 remains in the Trigger state until the Sync line is asserted. The Sync line may be asserted by a direct command or by any E1439 that encounters a trigger condition and is programmed to assert the Sync line. When the Sync signal is asserted, all modules synchronously move to the Measure state.

In the Measure state, the E1439 continues collecting data and sends the data saved in the FIFO memory to the selected I/O port, starting with the sample indicated by the trigger arrival, offset by the number of samples specified by the trigger delay. This data transfer continues until all data has been transferred or until the module meets the criteria for returning to the Idle state imposed by block mode or continuous mode operation constraints.

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