ARM Instruction Reference
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All r ights reserved. 4-7
4.2.1 LDR and STR, words and unsigned bytes
Load register and store register, 32-bit word or 8-bit unsigned byte. Byte loads are
zero-extended to 32 bits.
Syntax
Both
LDR
and
STR
have four possi ble forms:
•zero offset
•pre-indexed offset
•program-relative
•post-indexed offset.
The syntax of the four f orms, in the same ord er, are:
op{cond}{B}{T} Rd, [Rn]
op{cond}{B} Rd, [Rn, FlexOffset]{!}
op{cond}{B} Rd, label
op{cond}{B}{T} Rd, [Rn], FlexOffset
where:
op
is either
LDR
(Load Register) or
STR
(Store Register).
cond
is an optional condition code (see Conditional execution on page4-4).
B
is an optional suffix. If
B
is present, the least significant byte of
Rd
is
transferred. If
op
is
LDR
, the other bytes of
Rd
are cleared.
Otherwise, a 32-bit word is transferred.
T
is an optional suffix. If
T
is present, the memory sy stem treats the acce ss
as though the processor was in User mode, even if it is in a privileged
mode (see Processor mode on page2-4).
T
has no effect in User mode.
You cannot use
T
with a pre-indexed offset.
Rd
is the ARM register to load or save.
Rn
is the register on which the memory address is based.
Rn
must not be the same as
Rd
, if the instruction:
•is pre-indexed with writeback (the
!
suffix)
•is post-indexed
•uses the
T
suffix.