1 AND, ORR, EOR, and BIC, Range r0- r7 | ARM VERSION 1.2 specification

Thumb Instruction Reference

5.3.1AND, ORR, EOR, and BIC

Bitwise logical operations.

Syntax op Rd, Rm

where:
op	is one of AND, ORR, EOR, or BIC.
Rd	is the destination register. It also contains the first operand. Rd must be in
	the range r0-r7.
Rm	is the register containing the second operand. Rm must be in the range
	r0-r7.

Usage

These instructions perform a bitwise logical operation on the contents of Rd and Rm, and place the result in Rd. The operations are as follows:

•the AND instruction performs a logical AND operation

•the ORR instruction performs a logical OR operation

•the EOR instruction performs a logical Exclusive OR operation

•the BIC instruction performs an Rd AND NOT Rm operation.

Condition flags

These instructions update the N and Z flags according to the result. The C and V flags are not affected.

Architectures

These instructions are available in all T variants of the ARM architecture.

Example

AND r2,r4

ARM DUI 0068B

Copyright © 2000, 2001 ARM Limited. All rights reserved.

5-23

Image 217

ARM VERSION 1.2 1 AND, ORR, EOR, and BIC, Bitwise logical operations, Where Is one of AND, ORR, EOR, or BIC, Range r0- r7

Contents

ARM Developer Suite Assembler Guide ARM Developer SuiteCopyright 2000, 2001 ARM Limited. All rights reserved ARM Developer Suite Assembler Guide Glossary Feedback on About this book on About this book Using this bookIntended audience This book is organized into the following chapters Italic Typographical conventionsFurther reading ARM publications Other publications ARM Reference Peripheral Specification ARM DDI Feedback on the ARM Developer Suite FeedbackFeedback on this book ARM DUI 0068B About the ARM Developer Suite assemblers on Introduction ARM Developer Suite ADS has About the ARM Developer Suite assemblers Writing ARM and Thumb Assembly Language Code examples IntroductionOr run the module in AXD with interleaving on See Architecture versions Overview of the ARM architectureARM and Thumb state ARM processors always start executing code in ARM state Registers Processor modeGeneral-purpose, 32-bit registers Program counter pc Branch instructions ARM instruction set overviewData processing instructions Single register load and store instructions Status register access instructionsMultiple register load and store instructions Semaphore instructions Access to the inline barrel shifter Register accessARM instruction capabilities Following general points apply to ARM instructions Thumb instruction capabilities Thumb instruction set overviewFollowing general points apply to Thumb instructions Differences between Thumb and ARM instruction sets Access to the barrel shifter Single register load and store instructions Layout of assembly language source files Structure of assembly language modulesGeneral form of source lines in assembly language is Case rules Local labels LabelsComments Is a base between 2 Xxx is a number in that base Constants ELF sections and the Area directive An example ARM assembly language module Application execution Entry directiveApplication termination END directive Calling subroutines CODE32 and CODE16 directives An example Thumb assembly language moduleBX instruction Example 2-4 Preprocessing an assembly language source file Using the C preprocessor ALU status flags Conditional execution Examples Execution conditions Example of the use of conditional execution Using conditional execution in ARM state Conditional branches only Branch prediction and caches Converting to Thumb Loading constants into registers Right, 2 bits Direct loading with MOV and MVN Loading with LDR Rd, =const Direct loading with MOV in Thumb state Placing literal pools Loading floating-point constants Direct loading with ADR and Adrl Loading addresses into registers ADR Implementing a jump table with ADR Example 2-7 ARM code jump table Example 2-8 Thumb code jump table Loading addresses with LDR Rd, = label R1, =Darea + = LDR R1,PC, #offset into Literal Pool Address registers. For example, the instruction An LDR Rd, =label example string copyingIncrements r1 by Load register Load and store multiple register instructions Syntax ARM LDM and STM instructionsSyntax of the LDM instructions is Where LDM and STM addressing modes Usage Descending or ascending Implementing stacks with LDM and STM Stacking registers for nested subroutines Example 2-11 Block copy Block copy with LDM and STM Movs LDM and STM Thumb LDM and STM instructionsPush and POP Thumb-state block copy example LSR Test-and-branch macro example Using macrosThis macro can be invoked as follows After substitution this becomes Register that holds the divisor Unsigned integer division macro exampleAfter the instructions are executed, it holds the remainder If only the remainder is required Ratio DivMod r0,r5,r4,r2 Describing data structures with MAP and Field directives Relative maps Register-based maps Program-relative maps Finding the end of the allocated data Forcing correct alignment EndOfChars Defining register-based symbols Using register-based MAP and Field directives Is equivalent to the C code Setting up a C-type structure If you want the equivalent of the C code Making faster access possible2-27 for an explanation of these Not This example, the MAP directive is Field MAP Using two register-based structures Avoiding problems with MAP and Field directives ArrayBase RN r9 Using frame directives Expressions, literals, and operators on Symbols on Command syntax Position-independent. The default is /noropi Specifies that the content of inputfile is read-onlySpecifies that the content of inputfile is read-write Position-independent. The default is /norwpi Selection of libraries, accordingly Assembled for the wrong target FPUValid options are Selects no floating-point option. This makes your assembled Sets the maximum source cache size to n. The default is 8MB Command-line optionsObject file, for use by the debugger see Keep on Allow unaligned LDRs As \n and \t First pass and reads them from memory on the second passRegister names Turns off warning messages Assembler Reference Format of source lines Predeclared register names Predefined register and coprocessor namesPredeclared program status register names Predeclared floating-point register names Lists the built-in variables defined by the ARM assembler Built-in variablesExpressions or conditions, for example Determining the armasm version at assembly time Symbol naming rules SymbolsNumeric constants on Labels on Numeric constants Variables Gbls Assembly time substitution of variables DCD and Dcdu on Dcfd and Dcfdu on Dcfs and Dcfsu on Program-relative labelsDCQ and Dcqu on DCW and Dcwu on Register-relative labels Syntax of a reference to a local label is Syntax of a local label is Assembler Reference This section contains the following subsections Expressions, literals, and operators String literals String expressionsExample String literals Numeric expressions Numeric literals Is a sequence of characters using only the digits 0 to nNumeric literals can take any of the following forms Numeric code of the character Floating-point literals can take any of the following forms Floating-point literals Logical expressions Register-relative and program-relative expressionsLogical literals There are only two logical literals String manipulation Operator precedence Operator precedence in C Precedence Operator Usage Description Unary operators Example of use of SBOFFSET1912 and SBOFFSET11 Multiplicative operators Binary operatorsString manipulation operators SHR is a logical shift and does not propagate the sign bit Shift operatorsAddition, subtraction, and logical operators Relational operators 10 shows the Boolean operators Boolean operators ARM DUI 0068B ARM Instruction Reference Add with carry, Add All Logical Branch Move not All ARM condition codes Q flag LDR and STR, words and unsigned bytes on ARM memory access instructionsLDR and STR, halfwords and signed bytes on LDR and STR, doublewords on LDR and STR, words and unsigned bytes Where Is either LDR Load Register or STR Store RegisterOtherwise, a 32-bit word is transferred Pre-indexed offset Zero offsetProgram-relative Post-indexed offset Flexible offset syntax Loading to r15 Address alignment for word transfers Architectures Saving from r15 LDR and STR, halfwords and signed bytes Is an offset applied to the value in Rn see Offset syntax Must be within ±255 bytes of the current instructionOffset syntax Is often a numeric constant see examples below Address alignment for halfword transfers Offset syntax is the same for LDR and STR, doublewords onYou cannot load halfwords or bytes to r15 Incorrect example Is an optional condition code see Conditional execution on LDR and STR, doublewordsMust be an even numbered register, and not r14 Pre-indexed without writeback Address alignment Not be the same as Rd or Rd+1 Incorrect examples Is any one of the following Is either LDM or STMIncrement address after each transfer Increment address before each transfer Loading or storing the base register, with writeback Non word-aligned addresses Is the register on which the memory address is based 5 PLD Alignment 6 SWP Is swapped with the contents of the memory locationBoth Rd and Rm ARM general data processing instructions Flexible second operand Bits of the register are set to LSR and LSL Instruction substitution Carry flag Is one of ADD, SUB, RSB, ADC, SBC, or RSC 2 ADD, SUB, RSB, ADC, SBC, and RSCIs the ARM register for the result Is the ARM register holding the first operand Use of r15 Condition flagsMultiword arithmetic examples These instructions subtract one 96-bit integer from another Logical AND, OR, Exclusive or and Bit Clear 3 AND, ORR, EOR, and BICIs one of AND, ORR, EOR, or BIC Orreq Move and Move Not MOV and MVNIs the ARM register for the result Mvnne Compare and Compare Negative CMP and CMN CMN Test and Test Equivalence TST and TEQ TEQ Count Leading Zeroes 7 CLZIs the ARM register for the result. Rd must not be r15 Is the operand register MUL and MLA on ARM multiply instructionsUMULL, UMLAL, Smull and Smlal on MUL and MLA MUL Is one of UMULL, UMLAL, SMULL, or Smlal UMULL, UMLAL, Smull and Smlal Umull Use the top end bits 3116 of Rm SMULxyUse the top end bits 3116 of Rs Are the ARM registers holding the values to be multiplied Smulbt Is the ARM register holding the value to be added SMLAxy Smlatb Use the top end bits 3116 of Rs SMULWyAre the ARM registers holding the operands Are the ARM registers holding the values to be multiplied SMLAWyIs the ARM register holding the value to be added Smlawt SMLALxy Smlaltt Current processors 8 MIA, MIAPH, and MIAxyUse the top end bits 3116 of Rm R15 cannot be used for either Rm or Rs These instructions are only available in XScale QADD, QSUB, QDADD, and Qdsub ARM saturating arithmetic instructionsIs one of QADD, QSUB, QDADD, or Qdsub Are the ARM registers holding the operands Qadd ARM branch instructions Branch, and Branch with Link 2 BX 3 BLX Blxmi MCR, MCR2, Mcrr on ARM coprocessor instructions 1 CDP, CDP2 2 MCR, MCR2, Mcrr Is p n, where n is an integer in the rangeAre ARM source registers. They must not be r15 Affected 3 MRC, MRC2 Mrrc Is either LDC or STC 5 LDC, STCIs an optional suffix specifying a long transfer Is the coprocessor register to load or save Architectures Is either LDC2 or STC2 6 LDC2, STC2 Architectures Miscellaneous ARM instructions Software interrupt 1 SWI Where 2 MRSIs the destination register. Rd must not be r15 Is either Cpsr or Spsr Is either Cpsr or Spsr 3 MSRSee MRS on MSR CPSRf, r5 Breakpoint Bkpt For current processors 5 MAR, MRAAre general-purpose registers ADR ARM pseudo-instructionon ARM pseudo-instructionsAdrl ARM pseudo-instructionon LDR ARM pseudo-instruction on Is an optional condition code ADR ARM pseudo-instructionIs the register to load Non word-aligned address within ±255 bytes Non word-aligned address within 64KB Adrl ARM pseudo-instructionWord-aligned address within 256KB R4,start + = ADD R4,pc,#0xe800 LDR ARM pseudo-instruction R3,=0xff0 Loads Into = MOV r3,#0xff0 NOP ARM pseudo-instruction Thumb Instruction Reference Add with carry Rotate right LDR and STR, immediate offset on Thumb memory access instructionsLDR and STR, register offset on LDR and STR, pc or sp relative on LDR and STR, immediate offset Where Is eitherLoad register Store register Address alignment for word and halfword transfers LDR and STR, register offset Strsh 4 in the range 0 to LDR and STR, pc or sp relative R2,pc,#1016 POP reglist These instructions do not affect the flags POP reglist, pc Load and store multiple registers Ldmia and StmiaLoad multiple, increment after Store multiple, increment after R3!, r0,r4 ADD and SUB, sp on Thumb arithmetic instructionsADD, pc or sp relative on ADC, SBC, and MUL on To +7 ADD and SUB, low registers255 to +255 Restrictions These instructions update the N, Z, C, and V flags Is a register containing the second operand 2 ADD, high or low registers Range -508 to +508 ADD and SUB, sp Is the destination register. Rd must be in the range r0- r7 4 ADD, pc or sp relativeIs either sp or pc Range 5 ADC, SBC, and MUL Where Is one of ADC, SBC, or MUL CMP and CMN on page 5-26 Compare and Compare Negative Thumb general data processing instructionsMOV, MVN, and NEG on page 5-28 Move, Move NOT, and Negate TST on page 5-30 Test bits 1 AND, ORR, EOR, and BIC Where Is one of AND, ORR, EOR, or BICBitwise logical operations Range r0- r7 2 ASR, LSL, LSR, and ROR Immediate shift Register-controlled shift Where Is the register containing the first operand Examples 4 MOV, MVN, and NEG Where Is the destination registerMove, Move NOT, and Negate Is the source register Condition flags 5 TST Where Is the register containing the first operandTest bits Rn and Rm must be in the range r0-r7 Thumb branch instructions Is an optional condition code see -2 on 1 B3-23 for more information Label must be within Condition codes for Thumb B instruction Long branch with Link 2 BL 3 BX Branch with Link, and optionally exchange instruction set 4 BLXInstruction clears the T flag in the CPSR. Code at BLX label always causes a change to ARM state Bkpt on Thumb software interrupt and breakpoint instructions Bkpt immed8 Thumb pseudo-instructions 1KB. expr must be defined locally, it cannot be imported ADR Thumb pseudo-instruction If the value of expr is within range of a MOV instruction, LDR Thumb pseudo-instructionAssembler generates the instruction =labelname Syntax for NOP is NOP Thumb pseudo-instruction ARM DUI 0068B Vector Floating-point Programming Absolute value Vector All Negate Vector All Reference Manual Vector floating-point coprocessorVFP architectures Register banks Floating-point registers Vector wrap-around VectorsVector stride Restriction on vector length Control of scalar, vector and mixed operations Vector and scalar operationsScalar operations Vector operations VFP and condition codes Vector Floating-point Programming FPSCR, the floating-point status and control register VFP system registers 0b000 FPSID, the floating-point system ID register FPEXC, the floating-point exception registerModifying individual bits of a VFP system register See FMRX, FMXR, and Fmstat on When to use flush-to-zero mode Flush-to-zero modeEffects of using flush-to-zero mode Operations not affected by flush-to-zero mode Fmrrs and Fmsrr on VFP instructionsFMRX, FMXR, and Fmstat on Ftosi and Ftoui onPage Fabsd d3, d5 Fnegsmi s15, s15 Is the VFP register for the result Fadd and FsubIs the VFP register holding the first operand Is the VFP register holding the second operand Floating-point compare Fcmp is always scalar FcmpWith zero instruction Fcmp instructions can produce Invalid Operation exceptions Is a double-precision VFP register for the result FcvtdsIs a single-precision VFP register holding the operand Is a single-precision VFP register for the result FcvtsdIs a double-precision VFP register holding the operand Fdiv Floating-point load and store FLD and FSTPrecision specified in precision Address used for the transfer Fldsne Fldm and Fstm Following instructions are equivalent Unspecified precision Must be one of FMAC, FNMAC, FMSC, or Fnmsc FMAC, FNMAC, FMSC, and Fnmsc Fnmscsle Is the VFP double-precision register Fmdrr and FmrrdAre ARM registers. Do not use r15 These instructions do not produce any exceptions Is the ARM register. Rd must not be r15 FMDHR, FMDLR, FMRDH, and FmrdlThese instructions are used together as matched pairs Is the VFP single-precision register Fmrs and Fmsr Are two consecutive VFP single-precision registers Fmrrs and FmsrrAre the ARM registers. Do not use r15 Is the ARM register FMRX, FMXR, and Fmstat Fmul and Fnmul Fsito and Fuito Is the VFP register holding the operand Fsqrt Is a single-precision VFP register for the integer result Ftosi and Ftoui There is one VFP pseudo-instruction VFP pseudo-instructionFLD pseudo-instruction Can be S for single-precision, or D for double-precision D1,=3.12E106 Loads 3.12E106 into d1 Vfpassert Scalar on Vfpassert Vector on VFP directives and vector notation VFP directives and vector notation on Vfpassert Vector on Vfpassert Scalar VFP directives and vector notation on Vfpassert Scalar on Where Is the vector length Is the vector stride R10,FPSCR ARM DUI 0068B Conditional assembly, looping, inclusions, and macros Assembly control directives on Location of descriptions of directives Alphabetical list of directives This section describes the following directives Symbol definition directivesGBLA, GBLL, and Gbls on Declare a global arithmetic, logical, or string variable GBLA, GBLL, and Gbls Armasm -pd objectsize Seta 0xFF -o objectfile sourcefile LCLA, LCLL, and Lcls SETA, SETL, and Sets Names on Rlist CN directive defines a name for a coprocessor register 5 CNCoprocessor names on Evaluates to a coprocessor register number from 0 to Evaluates to a coprocessor number from 0 to 6 CP DN and SN Evaluates to a floating-point register number from 0 to 8 FN DCD and Dcdu on Data definition directivesDCQ and Dcqu on Ltorg Is a numeric or program-relative expression 2 MAPSet to this address During the first pass of the assembler By the value of expr FieldStorage counter Expressions on Space To 255 see Numeric expressions on 5 DCBQuoted string. The characters of the string are loaded into Consecutive bytes of store Numeric expression see Numeric expressions on DCD and DcduProgram-relative expression DCW and Dcwu on DCQ and Dcqu on Dcdo Dcfd and Dcfdu Dcfs and Dcfsu Is a numeric expression see Numeric expressions on 10 DCI DCD and Dcdu on DCW and Dcwu on DCQ and Dcqu To 65535 see Numeric expressions on DCW and DcwuDCD and Dcdu on DCQ and Dcqu on Data Macro and Mend on Assembly control directivesMexit on IF, ELSE, and Endif on While and Wend on Macro and Mend BGE Mexit Using a macro to produce assembly-time diagnostics See Relational operators on 4 IF, ELSE, and Endif Example 7-3 Assembly conditional on a variable being defined While and Wend Frame description directives Frame Register on Frame Restore onFrame Address on Frame POP on Frame Push on Can omit it Is sp unless the function uses a separate frame pointer Is the number of bytes that the stack pointer moves There are two alternative syntaxes for Frame POP There are two alternative syntaxes for Frame Push Frame Push Is the register in which the value is preserved Frame Register Frame Restore Frame Save Frame State Remember Frame State Restore on Function or Proc on Frame State Remember on Function or Proc on Frame State Restore Function or Proc Endfunc or Endp Assert Reporting directivesIs an assertion that can evaluate to either True or False Is an expression that evaluates to a string Info 3 OPT Where Is the OPT directive setting. -2 lists valid settingsSpecify the -listassembler option to turn on listing OPT Is the title TTL and SubtIs the subtitle CODE16 and CODE32 on Miscellaneous directivesExport or Global on GET or Include on Align Cacheable, CODE, ALIGN=3 Area Example,CODE,READONLY An example code section CODE16 and CODE32 4 END Entry directive declares an entry point to a program Entry 6 EQU Is the symbolic name to assign to the valueAddress, or a 32-bit integer constant Is optional. type can be any one Export or Global Exportas Extern Nesting directives on GET or Include Global File, or library. The symbol name is case-sensitiveSee Export or Global on Import Include IncbinSee GET or Include on Keep Symbols are kept except register-relative symbols Nofp Assembly failsRequire Require directive specifies a dependency between sections REQUIRE8 and PRESERVE8 Evaluates to a register number from 0 to 19 RN Rout Among other things, computer software See ARM Developer SuiteThumb state Platforms Default thread runs Used to find errors in the application program flowSee also Saved Processor Status Register Otherwise stated See also Rwpi See also RopiSee Read Only Position Independent See Read Write Position Independent Block of software code or data for an Image Normally set to zero on resetBy ARM to handle semihosting See Saved Processor Status Register Index Align Gbll Adrl Symbols Index-6