ARM VERSION 1.2 - page 113

ARM Instruction Reference
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All r ights reserved. 4-3
MUL Multiply page 4-40 2
MVN Move not page4-32 All
ORR Logical OR page4-30 All
PLD Cache preload page 4-20 5Ed
QADD , QDADD , QDSUB , QSUB Saturating arithmetic page4-55 5ExPe
RSB , RSC , SBC Reverse sub, Reverse sub with carry, Sub with carry page4-27 All
SMLAL Signed multiply-accumulate (64 <= 32 x 32 + 64) page4-42 Mf
SMLALxy Signed multiply-accumulate (64 <= 16 x 16 + 64) page4-51 5ExPe
SMLAWy Signed multiply-accumulate (32 <= 32 x 16 + 32) page4-49 5ExPe
SMLAxy Signed multiply-accumulate (32 <= 16 x 16 + 32) page4-46 5ExPe
SMULL Signed multiply (64 <= 32 x 32) page4-42 Mf
SMULWy Signed multiply (32 <= 32 x 16) page4-48 5ExPe
SMULxy Signed multiply (32 <= 16 x 16) page4-44 5ExPe
STC , STC2 Store coprocessor page4-67 2, 5ExPe
STM Store multiple registers page 4-18 All
STR Store register page 4-6 All
SUB Subtract page4-27 All
SWI Software interrupt page4-72 All
SWP Swap registers and memory page4-22 3
TEQ , TST Test equivalence, Test page 4-36 All
UMLAL , UMULL Unsigned MLA, MUL (64 <= 32 x 32 (+ 64)) page4-42 Mf
a. n : available in ARM architecture version n and above
b. nT : available in T variants of ARM architecture version n and above
c. XScale: XScale coprocessor instructions
d. nE : available in E variants of ARM architecture version n and above, except ExP variants
e. nE : available in all E variants of ARM architecture version n and above, includ ing ExP varian ts
f. M : available in ARM architecture version 3M, and 4 and above, except xM versions
Table4-1 Location of ARM instructions (continued)
Mnemonic Brief description Page Architecturea