ARM Developer Suite
ARM Developer Suite
Assembler Guide
Copyright 2000, 2001 ARM Limited. All rights reserved
ARM Developer Suite Assembler Guide
Glossary
Feedback on
About this book on
This book is organized into the following chapters
Using this book
About this book
Intended audience
ARM publications
Typographical conventions
Italic
Further reading
Other publications
ARM Reference Peripheral Specification ARM DDI
Feedback
Feedback on the ARM Developer Suite
Feedback on this book
ARM DUI 0068B
About the ARM Developer Suite assemblers on
Introduction
ARM Developer Suite ADS has
About the ARM Developer Suite assemblers
Writing ARM and Thumb Assembly Language
Introduction
Code examples
Or run the module in AXD with interleaving on See
ARM processors always start executing code in ARM state
Overview of the ARM architecture
Architecture versions
ARM and Thumb state
Processor mode
Registers
General-purpose, 32-bit registers
Program counter pc
ARM instruction set overview
Branch instructions
Data processing instructions
Semaphore instructions
Status register access instructions
Single register load and store instructions
Multiple register load and store instructions
Following general points apply to ARM instructions
Register access
Access to the inline barrel shifter
ARM instruction capabilities
Thumb instruction set overview
Thumb instruction capabilities
Following general points apply to Thumb instructions
Differences between Thumb and ARM instruction sets
Access to the barrel shifter
Single register load and store instructions
Case rules
Structure of assembly language modules
Layout of assembly language source files
General form of source lines in assembly language is
Labels
Local labels
Comments
Is a base between 2 Xxx is a number in that base
Constants
ELF sections and the Area directive
An example ARM assembly language module
END directive
Entry directive
Application execution
Application termination
Calling subroutines
An example Thumb assembly language module
CODE32 and CODE16 directives
BX instruction
Example 2-4 Preprocessing an assembly language source file
Using the C preprocessor
ALU status flags
Conditional execution
Examples
Execution conditions
Example of the use of conditional execution
Using conditional execution in ARM state
Conditional branches only
Branch prediction and caches
Converting to Thumb
Loading constants into registers
Right, 2 bits
Direct loading with MOV and MVN
Loading with LDR Rd, =const
Direct loading with MOV in Thumb state
Placing literal pools
Loading floating-point constants
Direct loading with ADR and Adrl
Loading addresses into registers
ADR
Implementing a jump table with ADR
Example 2-7 ARM code jump table
Example 2-8 Thumb code jump table
Loading addresses with LDR Rd, = label
R1, =Darea + = LDR R1,PC, #offset into Literal Pool
An LDR Rd, =label example string copying
Address registers. For example, the instruction
Increments r1 by
Load register
Load and store multiple register instructions
Where
ARM LDM and STM instructions
Syntax
Syntax of the LDM instructions is
LDM and STM addressing modes
Usage
Descending or ascending
Implementing stacks with LDM and STM
Stacking registers for nested subroutines
Example 2-11 Block copy
Block copy with LDM and STM
Movs
Thumb-state block copy example
Thumb LDM and STM instructions
LDM and STM
Push and POP
LSR
After substitution this becomes
Using macros
Test-and-branch macro example
This macro can be invoked as follows
If only the remainder is required
Unsigned integer division macro example
Register that holds the divisor
After the instructions are executed, it holds the remainder
Ratio DivMod r0,r5,r4,r2
Describing data structures with MAP and Field directives
Relative maps
Register-based maps
Program-relative maps
Finding the end of the allocated data
Forcing correct alignment
EndOfChars
Defining register-based symbols
Using register-based MAP and Field directives
Is equivalent to the C code
Setting up a C-type structure
Making faster access possible
If you want the equivalent of the C code
2-27 for an explanation of these
Not
This example, the MAP directive is
Field MAP
Using two register-based structures
Avoiding problems with MAP and Field directives
ArrayBase RN r9
Using frame directives
Expressions, literals, and operators on
Symbols on
Command syntax
Position-independent. The default is /norwpi
Specifies that the content of inputfile is read-only
Position-independent. The default is /noropi
Specifies that the content of inputfile is read-write
Selects no floating-point option. This makes your assembled
Assembled for the wrong target FPU
Selection of libraries, accordingly
Valid options are
Allow unaligned LDRs
Command-line options
Sets the maximum source cache size to n. The default is 8MB
Object file, for use by the debugger see Keep on
Turns off warning messages
First pass and reads them from memory on the second pass
As \n and \t
Register names
Assembler Reference
Format of source lines
Predeclared floating-point register names
Predefined register and coprocessor names
Predeclared register names
Predeclared program status register names
Built-in variables
Lists the built-in variables defined by the ARM assembler
Expressions or conditions, for example
Determining the armasm version at assembly time
Labels on
Symbols
Symbol naming rules
Numeric constants on
Numeric constants
Variables
Gbls
Assembly time substitution of variables
Register-relative labels
Program-relative labels
DCD and Dcdu on Dcfd and Dcfdu on Dcfs and Dcfsu on
DCQ and Dcqu on DCW and Dcwu on
Syntax of a reference to a local label is
Syntax of a local label is
Assembler Reference
This section contains the following subsections
Expressions, literals, and operators
String literals
String expressions
String literals
Example
Numeric expressions
Numeric code of the character
Is a sequence of characters using only the digits 0 to n
Numeric literals
Numeric literals can take any of the following forms
Floating-point literals can take any of the following forms
Floating-point literals
There are only two logical literals
Register-relative and program-relative expressions
Logical expressions
Logical literals
String manipulation
Operator precedence
Operator precedence in C Precedence
Operator Usage Description
Unary operators
Example of use of SBOFFSET1912 and SBOFFSET11
Binary operators
Multiplicative operators
String manipulation operators
Shift operators
SHR is a logical shift and does not propagate the sign bit
Addition, subtraction, and logical operators
Relational operators
10 shows the Boolean operators
Boolean operators
ARM DUI 0068B
ARM Instruction Reference
Add with carry, Add All Logical Branch
Move not All
ARM condition codes
Q flag
LDR and STR, doublewords on
ARM memory access instructions
LDR and STR, words and unsigned bytes on
LDR and STR, halfwords and signed bytes on
Where Is either LDR Load Register or STR Store Register
LDR and STR, words and unsigned bytes
Otherwise, a 32-bit word is transferred
Post-indexed offset
Zero offset
Pre-indexed offset
Program-relative
Flexible offset syntax
Loading to r15
Address alignment for word transfers
Architectures
Saving from r15
LDR and STR, halfwords and signed bytes
Is often a numeric constant see examples below
Must be within ±255 bytes of the current instruction
Is an offset applied to the value in Rn see Offset syntax
Offset syntax
Incorrect example
Offset syntax is the same for LDR and STR, doublewords on
Address alignment for halfword transfers
You cannot load halfwords or bytes to r15
Pre-indexed without writeback
LDR and STR, doublewords
Is an optional condition code see Conditional execution on
Must be an even numbered register, and not r14
Address alignment
Not be the same as Rd or Rd+1
Incorrect examples
Increment address before each transfer
Is either LDM or STM
Is any one of the following
Increment address after each transfer
Loading or storing the base register, with writeback
Non word-aligned addresses
Is the register on which the memory address is based
5 PLD
Alignment
Is swapped with the contents of the memory location
6 SWP
Both Rd and Rm
ARM general data processing instructions
Flexible second operand
Bits of the register are set to
LSR and LSL
Instruction substitution
Carry flag
Is the ARM register holding the first operand
2 ADD, SUB, RSB, ADC, SBC, and RSC
Is one of ADD, SUB, RSB, ADC, SBC, or RSC
Is the ARM register for the result
Condition flags
Use of r15
Multiword arithmetic examples
These instructions subtract one 96-bit integer from another
3 AND, ORR, EOR, and BIC
Logical AND, OR, Exclusive or and Bit Clear
Is one of AND, ORR, EOR, or BIC
Orreq
MOV and MVN
Move and Move Not
Is the ARM register for the result
Mvnne
Compare and Compare Negative
CMP and CMN
CMN
Test and Test Equivalence
TST and TEQ
TEQ
Is the operand register
7 CLZ
Count Leading Zeroes
Is the ARM register for the result. Rd must not be r15
ARM multiply instructions
MUL and MLA on
UMULL, UMLAL, Smull and Smlal on
MUL and MLA
MUL
Is one of UMULL, UMLAL, SMULL, or Smlal
UMULL, UMLAL, Smull and Smlal
Umull
Are the ARM registers holding the values to be multiplied
SMULxy
Use the top end bits 3116 of Rm
Use the top end bits 3116 of Rs
Smulbt
Is the ARM register holding the value to be added
SMLAxy
Smlatb
SMULWy
Use the top end bits 3116 of Rs
Are the ARM registers holding the operands
SMLAWy
Are the ARM registers holding the values to be multiplied
Is the ARM register holding the value to be added
Smlawt
SMLALxy
Smlaltt
R15 cannot be used for either Rm or Rs
8 MIA, MIAPH, and MIAxy
Current processors
Use the top end bits 3116 of Rm
These instructions are only available in XScale
Are the ARM registers holding the operands
ARM saturating arithmetic instructions
QADD, QSUB, QDADD, and Qdsub
Is one of QADD, QSUB, QDADD, or Qdsub
Qadd
ARM branch instructions
Branch, and Branch with Link
2 BX
3 BLX
Blxmi
MCR, MCR2, Mcrr on
ARM coprocessor instructions
1 CDP, CDP2
Is p n, where n is an integer in the range
2 MCR, MCR2, Mcrr
Are ARM source registers. They must not be r15
Affected
3 MRC, MRC2
Mrrc
Is the coprocessor register to load or save
5 LDC, STC
Is either LDC or STC
Is an optional suffix specifying a long transfer
Architectures
Is either LDC2 or STC2
6 LDC2, STC2
Architectures
Miscellaneous ARM instructions
Software interrupt
1 SWI
Is either Cpsr or Spsr
2 MRS
Where
Is the destination register. Rd must not be r15
3 MSR
Is either Cpsr or Spsr
See MRS on
MSR CPSRf, r5
Breakpoint
Bkpt
5 MAR, MRA
For current processors
Are general-purpose registers
LDR ARM pseudo-instruction on
ARM pseudo-instructions
ADR ARM pseudo-instructionon
Adrl ARM pseudo-instructionon
Non word-aligned address within ±255 bytes
ADR ARM pseudo-instruction
Is an optional condition code
Is the register to load
Adrl ARM pseudo-instruction
Non word-aligned address within 64KB
Word-aligned address within 256KB
R4,start + = ADD R4,pc,#0xe800
LDR ARM pseudo-instruction
R3,=0xff0 Loads Into = MOV r3,#0xff0
NOP ARM pseudo-instruction
Thumb Instruction Reference
Add with carry
Rotate right
LDR and STR, pc or sp relative on
Thumb memory access instructions
LDR and STR, immediate offset on
LDR and STR, register offset on
Store register
Where Is either
LDR and STR, immediate offset
Load register
Address alignment for word and halfword transfers
LDR and STR, register offset
Strsh
4 in the range 0 to
LDR and STR, pc or sp relative
R2,pc,#1016
POP reglist
These instructions do not affect the flags
POP reglist, pc
Store multiple, increment after
Ldmia and Stmia
Load and store multiple registers
Load multiple, increment after
R3!, r0,r4
ADC, SBC, and MUL on
Thumb arithmetic instructions
ADD and SUB, sp on
ADD, pc or sp relative on
ADD and SUB, low registers
To +7
255 to +255
Restrictions
These instructions update the N, Z, C, and V flags
Is a register containing the second operand
2 ADD, high or low registers
Range -508 to +508
ADD and SUB, sp
Range
4 ADD, pc or sp relative
Is the destination register. Rd must be in the range r0- r7
Is either sp or pc
5 ADC, SBC, and MUL
Where Is one of ADC, SBC, or MUL
TST on page 5-30 Test bits
Thumb general data processing instructions
CMP and CMN on page 5-26 Compare and Compare Negative
MOV, MVN, and NEG on page 5-28 Move, Move NOT, and Negate
Range r0- r7
Where Is one of AND, ORR, EOR, or BIC
1 AND, ORR, EOR, and BIC
Bitwise logical operations
2 ASR, LSL, LSR, and ROR
Immediate shift
Register-controlled shift
Where Is the register containing the first operand
Examples
Is the source register
Where Is the destination register
4 MOV, MVN, and NEG
Move, Move NOT, and Negate
Condition flags
Rn and Rm must be in the range r0-r7
Where Is the register containing the first operand
5 TST
Test bits
Thumb branch instructions
Label must be within
1 B
Is an optional condition code see -2 on
3-23 for more information
Condition codes for Thumb B instruction
Long branch with Link
2 BL
3 BX
BLX label always causes a change to ARM state
4 BLX
Branch with Link, and optionally exchange instruction set
Instruction clears the T flag in the CPSR. Code at
Bkpt on
Thumb software interrupt and breakpoint instructions
Bkpt immed8
Thumb pseudo-instructions
1KB. expr must be defined locally, it cannot be imported
ADR Thumb pseudo-instruction
LDR Thumb pseudo-instruction
If the value of expr is within range of a MOV instruction,
Assembler generates the instruction
=labelname
Syntax for NOP is
NOP Thumb pseudo-instruction
ARM DUI 0068B
Vector Floating-point Programming
Absolute value Vector All
Negate Vector All
Vector floating-point coprocessor
Reference Manual
VFP architectures
Register banks
Floating-point registers
Restriction on vector length
Vectors
Vector wrap-around
Vector stride
Vector operations
Vector and scalar operations
Control of scalar, vector and mixed operations
Scalar operations
VFP and condition codes
Vector Floating-point Programming
FPSCR, the floating-point status and control register
VFP system registers
0b000
See FMRX, FMXR, and Fmstat on
FPEXC, the floating-point exception register
FPSID, the floating-point system ID register
Modifying individual bits of a VFP system register
Flush-to-zero mode
When to use flush-to-zero mode
Effects of using flush-to-zero mode
Operations not affected by flush-to-zero mode
Ftosi and Ftoui on
VFP instructions
Fmrrs and Fmsrr on
FMRX, FMXR, and Fmstat on
Page
Fabsd d3, d5 Fnegsmi s15, s15
Is the VFP register holding the second operand
Fadd and Fsub
Is the VFP register for the result
Is the VFP register holding the first operand
Fcmp instructions can produce Invalid Operation exceptions
Fcmp
Floating-point compare Fcmp is always scalar
With zero instruction
Fcvtds
Is a double-precision VFP register for the result
Is a single-precision VFP register holding the operand
Fcvtsd
Is a single-precision VFP register for the result
Is a double-precision VFP register holding the operand
Fdiv
Address used for the transfer
FLD and FST
Floating-point load and store
Precision specified in precision
Fldsne
Fldm and Fstm
Following instructions are equivalent
Unspecified precision
Must be one of FMAC, FNMAC, FMSC, or Fnmsc
FMAC, FNMAC, FMSC, and Fnmsc
Fnmscsle
These instructions do not produce any exceptions
Fmdrr and Fmrrd
Is the VFP double-precision register
Are ARM registers. Do not use r15
FMDHR, FMDLR, FMRDH, and Fmrdl
Is the ARM register. Rd must not be r15
These instructions are used together as matched pairs
Is the VFP single-precision register
Fmrs and Fmsr
Fmrrs and Fmsrr
Are two consecutive VFP single-precision registers
Are the ARM registers. Do not use r15
Is the ARM register
FMRX, FMXR, and Fmstat
Fmul and Fnmul
Fsito and Fuito
Is the VFP register holding the operand
Fsqrt
Is a single-precision VFP register for the integer result
Ftosi and Ftoui
Can be S for single-precision, or D for double-precision
VFP pseudo-instruction
There is one VFP pseudo-instruction
FLD pseudo-instruction
D1,=3.12E106 Loads 3.12E106 into d1
Vfpassert Scalar on Vfpassert Vector on
VFP directives and vector notation
VFP directives and vector notation on Vfpassert Vector on
Vfpassert Scalar
VFP directives and vector notation on Vfpassert Scalar on
Where Is the vector length Is the vector stride
R10,FPSCR
ARM DUI 0068B
Conditional assembly, looping, inclusions, and macros
Assembly control directives on
Location of descriptions of directives
Alphabetical list of directives
Declare a global arithmetic, logical, or string variable
Symbol definition directives
This section describes the following directives
GBLA, GBLL, and Gbls on
GBLA, GBLL, and Gbls
Armasm -pd objectsize Seta 0xFF -o objectfile sourcefile
LCLA, LCLL, and Lcls
SETA, SETL, and Sets
Names on
Rlist
Evaluates to a coprocessor register number from 0 to
5 CN
CN directive defines a name for a coprocessor register
Coprocessor names on
Evaluates to a coprocessor number from 0 to
6 CP
DN and SN
Evaluates to a floating-point register number from 0 to
8 FN
Data definition directives
DCD and Dcdu on
DCQ and Dcqu on
Ltorg
During the first pass of the assembler
2 MAP
Is a numeric or program-relative expression
Set to this address
Field
By the value of expr
Storage counter
Expressions on
Space
Consecutive bytes of store
5 DCB
To 255 see Numeric expressions on
Quoted string. The characters of the string are loaded into
DCW and Dcwu on DCQ and Dcqu on
DCD and Dcdu
Numeric expression see Numeric expressions on
Program-relative expression
Dcdo
Dcfd and Dcfdu
Dcfs and Dcfsu
Is a numeric expression see Numeric expressions on
10 DCI
DCD and Dcdu on DCW and Dcwu on
DCQ and Dcqu
Data
DCW and Dcwu
To 65535 see Numeric expressions on
DCD and Dcdu on DCQ and Dcqu on
IF, ELSE, and Endif on While and Wend on
Assembly control directives
Macro and Mend on
Mexit on
Macro and Mend
BGE
Mexit
Using a macro to produce assembly-time diagnostics
See Relational operators on
4 IF, ELSE, and Endif
Example 7-3 Assembly conditional on a variable being defined
While and Wend
Frame POP on Frame Push on
Frame Register on Frame Restore on
Frame description directives
Frame Address on
Can omit it
Is sp unless the function uses a separate frame pointer
Is the number of bytes that the stack pointer moves
There are two alternative syntaxes for Frame POP
There are two alternative syntaxes for Frame Push
Frame Push
Is the register in which the value is preserved
Frame Register
Frame Restore
Frame Save
Frame State Remember
Frame State Restore on Function or Proc on
Frame State Remember on Function or Proc on
Frame State Restore
Function or Proc
Endfunc or Endp
Reporting directives
Assert
Is an assertion that can evaluate to either True or False
Is an expression that evaluates to a string
Info
Where Is the OPT directive setting. -2 lists valid settings
3 OPT
Specify the -listassembler option to turn on listing
OPT
TTL and Subt
Is the title
Is the subtitle
GET or Include on
Miscellaneous directives
CODE16 and CODE32 on
Export or Global on
Align
Cacheable, CODE, ALIGN=3
Area
Example,CODE,READONLY An example code section
CODE16 and CODE32
4 END
Entry directive declares an entry point to a program
Entry
Is optional. type can be any one
Is the symbolic name to assign to the value
6 EQU
Address, or a 32-bit integer constant
Export or Global
Exportas
Extern
Nesting directives on
GET or Include
Import
File, or library. The symbol name is case-sensitive
Global
See Export or Global on
Incbin
Include
See GET or Include on
Keep
Symbols are kept except register-relative symbols
Require directive specifies a dependency between sections
Assembly fails
Nofp
Require
REQUIRE8 and PRESERVE8
Evaluates to a register number from 0 to
19 RN
Rout
Platforms
See ARM Developer Suite
Among other things, computer software
Thumb state
Otherwise stated
Used to find errors in the application program flow
Default thread runs
See also Saved Processor Status Register
See Read Write Position Independent
See also Ropi
See also Rwpi
See Read Only Position Independent
See Saved Processor Status Register
Normally set to zero on reset
Block of software code or data for an Image
By ARM to handle semihosting
Index
Align
Gbll
Adrl
Symbols
Index-6