Thumb Instruction Referenc e
5-8 Copyright © 2000, 20 01 ARM Limited. All rights reserved. ARM DUI 0068B
Address alignment for word and halfword transfers
The address must be divisible by 4 for word transfers, and by 2 for halfword transfers.
If your system has a system coprocessor (cp15), you can enable alignment checking.
Non-aligned transfers cause an alignment exception if alignment checking is enabled.
If your system does not have a system coprocessor (cp15), or alignment checking is
disabled:
•A non-aligned load corrupts
Rd
.
•A non-aligned save corrupts memory. The corrupted location in memory is the
halfword at [address AND NOT 0x1] for halfword saves, and the word at [address
AND NOT b11] for word saves.
Architectures
These instructions are availabl e in all T variants of the ARM archite cture.
Examples
LDR r2,[r1,r5]
LDRSH r0,[r0,r6]
STRB r1,[r7,r0]
Incorrect examples
LDR r13,[r5,r3] ; high registers not allowed
STRSH r7,[r3,r1] ; no signed store instruction