ARM VERSION 1.2

Writing ARM and Thumb Assembly Language

Example2-27 on page 2-64 loads the first six items in the array

Misc_data

. The array is

a single element and therefore covers contiguous memory locations. No one is likely to

want to split it into separa te arrays in the future.

However, for loading

Misc_I

Misc_J

, and

Misc_K

into registers r0, r1, and r2 the

following code works, but might cause problems in the future:

ArrayBase RN r9

ADR ArrayBase, Misc_I

LDMIA ArrayBase, {r0-r2}

Problems arise if the order of

Misc_I

Misc_J

, and

Misc_K

is changed, or if a new element

Misc_New

is added in the middle. Either of these small changes breaks the code.

If these elements are accessed separately elsewhere, you must not amalgamate them

into a single array element. In this case, you must amend the code. The first remedy is

to comment the struct ure to prevent changes affecting this section :

Misc_I FIELD 4 ; ==} Do not split/reorder

Misc_J FIELD 4 ; } these 3 elements, STM

Misc_K FIELD 4 ; ==} and LDM instructions used.

If the code is strongly commented, no deliberate changes are likely to be made that

affect the workings of the program. Unfortunately, mistakes can occur. A second

method of catching these problems is to add

ASSERT

directives just before the

STM

and

LDM

instructions to check that the labels are consecutive and in the correct order:

ArrayBase RN R9

; Check that the structure elements

; are correctly ordered for LDM

ASSERT (((Misc_J-Misc_I) = 4) :LAND: ((Misc_K-Misc_J) = 4))

ADR ArrayBase, Misc_I

LDMIA ArrayBase, {r0-r2}

This

ASSERT

directive stops assembly at this point if the structure is not in the correct

order to be loaded with an

LDM

. Remember that the e lement with the lowes t address is

always loaded from, or stored to, the lowest numbered register.