ARM VERSION 1.2 - page 112

ARM Instruction Reference
4-2 Copyright © 2000, 20 01 ARM Limited. All rights reserved. ARM DUI 0068B
Table4-1 Location of ARM instructions
Mnemonic Brief description Page Architecturea
ADC , ADD Add with carry, Add page4-27 All
AND Logical AND page4-30 All
B Branch page4-58 All
BIC Bit clear page4-30 All
BKPT Breakpoint page4-76 5
BL Branch with link page4-58 All
BLX Branch, link and exchange page4-60 5Tb
BX Branch and exchange page4-59 4Tb
CDP , CDP2 Coprocessor data operation page4-63 2, 5
CLZ Count leading zeroes page 4-38 5
CMN , CMP Compare negative, Compare page4-34 All
EOR Exclusive OR page4-30 All
LDC , LDC2 Load coprocessor page4-67 2, 5
LDM Load multiple registers page4-18 All
LDR Load register page 4-6 All
MAR Move from registers to 40-bit accumulator page4-77 XScalec
MCR , MCR2 , MCRR Move from register(s) to coprocessor page4-64 2, 5, 5Ed
MIA , MIAPH , MIAxy Multiply with internal 40-bit accumulate page 4-53 XScale
MLA Multiply accumulate page4 -40 2
MOV Move page 4-32 All
MRA Move from 40-bit accumulator to registers page4-77 XScale
MRC , MRC2 Move from coprocessor to register page4-65 2, 5
MRRC Move from coprocessor to 2 registers page4-66 5Ed
MRS Move from PSR to regi ster pa ge 4-73 3
MSR Move from register to PSR page4-74 3