ARM VERSION 1.2

Writing ARM and Thumb Assembly Language

Placing literal poo ls

The assembler places a literal pool at the end of each section. These are defined by the

AREA

directive at the star t of the following s ection, or by the

END

directive at the end of

the assembly. The

END

directive at the end of an included file does not signal the end of

a section.

In large sections the default literal pool can be out of range of one or more

LDR

instructions. The offset from the pc to the constant must be:

•less than 4KB in ARM state, but can be in either direction

•forward and less than 1KB in Thumb state.

When an

LDR Rd,=const

pseudo-instruction requires the constant to be placed in a literal

pool, the assembler :

•Checks if the constant is available and addressable in any previous literal pools.

If so, it addresses the existing constant.

•Attempts to place the constant in the next literal pool if it is not already available.

If the next literal pool is out of range, the assembler generates an error message. In this

case you must use the

LTORG

directive to place an additional literal pool in the code. Place

the

LTORG

directive after the failed

LDR

pseudo-instruction, and within 4KB (ARM) or

1KB (Thumb). Refer to LTORG on page 7-14 for a detailed description.

You must place literal pools where the processor does not attempt to execute them as

instructions. Place them after unconditional branch instructions, or after the return

instruction at the end of a subroutine.

Example2-5 shows how this works in practice. It is supplied as

loadcon.s

in the

examples\asm

subdirectory of the ADS. The instructions listed as comments are the

ARM instructions that are generated by the assembler. Refer to Code examples on

page2-2 for instructions on how to assemble, link, and execute the example.

Example2-5

AREA Loadcon, CODE, READONLY

ENTRY ; Mark first instruction to execute

start BL func1 ; Branch to first subroutine

BL func2 ; Branch to second subroutine

stop MOV r0, #0x18 ; angel_SWIreason_ReportException

LDR r1, =0x20026 ; ADP_Stopped_ApplicationExit

SWI 0x123456 ; ARM semihosting SWI

func1

LDR r0, =42 ; => MOV R0, #42

LDR r1, =0x55555555 ; => LDR R1, [PC, #offset to

; Literal Pool 1]