Manuals / ARM / Computer Equipment / Computer Hardware

ARM VERSION 1.2 manual Implementing stacks with LDM and STM, Descending or ascending

Models: VERSION 1.2

1 360

Download 360 pages 38.37 Kb

Page 54

Writing ARM and Thumb Assembly Language

2.8.3Implementing stacks with LDM and STM

The load and store multiple instructions can update the base register. For stack operations, the base register is usually the stack pointer, r13. This means that you can use load and store multiple instructions to implement push and pop operations for any number of registers in a single instruction.

The load and store multiple instructions can be used with several types of stack:

Descending or ascending

The stack grows downwards, starting with a high address and progressing to a lower one (a descending stack), or upwards, starting from a low address and progressing to a higher address (an ascending stack).

Full or empty

The stack pointer can either point to the last item in the stack (a full stack), or the next free space on the stack (an empty stack).

To make it easier for the programmer, stack-oriented suffixes can be used instead of the increment or decrement and before or after suffixes. Refer to Table 2-5 for a list of stack-oriented suffixes.

Table 2-5 Suffixes for load and store multiple instructions

Stack type	Push	Pop

Full descending	STMFD (STMDB)	LDMFD (LDMIA)

Full ascending	STMFA (STMIB)	LDMFA (LDMDA)

Empty descending	STMED (STMDA)	LDMED (LDMIB)

Empty ascending	STMEA (STMIA)	LDMEA (LDMDB)

For example:

STMFD	r13!,	{r0-r5}	;	Push onto a Full Descending Stack
LDMFD	r13!,	{r0-r5}	;	Pop from a Full Descending Stack.

Note

The ARM-Thumb Procedure Call Standard (ATPCS), and ARM and Thumb C and C++ compilers always use a full descending stack.

2-42

Copyright © 2000, 2001 ARM Limited. All rights reserved.

ARM DUI 0068B

Image 54

ARM VERSION 1.2 manual Implementing stacks with LDM and STM, Descending or ascending

Contents

ARM Developer Suite ARM Developer Suite Assembler GuideCopyright 2000, 2001 ARM Limited. All rights reserved ARM Developer Suite Assembler Guide Glossary About this book on Feedback onIntended audience Using this bookAbout this book This book is organized into the following chaptersFurther reading Typographical conventionsItalic ARM publicationsARM Reference Peripheral Specification ARM DDI Other publicationsFeedback Feedback on the ARM Developer SuiteFeedback on this book ARM DUI 0068B Introduction About the ARM Developer Suite assemblers onAbout the ARM Developer Suite assemblers ARM Developer Suite ADS hasWriting ARM and Thumb Assembly Language Introduction Code examplesOr run the module in AXD with interleaving on See ARM and Thumb state Overview of the ARM architectureArchitecture versions ARM processors always start executing code in ARM stateProcessor mode RegistersGeneral-purpose, 32-bit registers Program counter pc ARM instruction set overview Branch instructionsData processing instructions Multiple register load and store instructions Status register access instructionsSingle register load and store instructions Semaphore instructionsARM instruction capabilities Register accessAccess to the inline barrel shifter Following general points apply to ARM instructionsThumb instruction set overview Thumb instruction capabilitiesFollowing general points apply to Thumb instructions Access to the barrel shifter Differences between Thumb and ARM instruction setsSingle register load and store instructions General form of source lines in assembly language is Structure of assembly language modulesLayout of assembly language source files Case rulesLabels Local labelsComments Constants Is a base between 2 Xxx is a number in that baseAn example ARM assembly language module ELF sections and the Area directiveApplication termination Entry directiveApplication execution END directiveCalling subroutines An example Thumb assembly language module CODE32 and CODE16 directivesBX instruction Using the C preprocessor Example 2-4 Preprocessing an assembly language source fileConditional execution ALU status flagsExecution conditions ExamplesUsing conditional execution in ARM state Example of the use of conditional executionConditional branches only Converting to Thumb Branch prediction and cachesLoading constants into registers Direct loading with MOV and MVN Right, 2 bitsDirect loading with MOV in Thumb state Loading with LDR Rd, =constPlacing literal pools Loading floating-point constants Loading addresses into registers Direct loading with ADR and AdrlADR Implementing a jump table with ADR Example 2-7 ARM code jump table Example 2-8 Thumb code jump table Loading addresses with LDR Rd, = label R1, =Darea + = LDR R1,PC, #offset into Literal Pool An LDR Rd, =label example string copying Address registers. For example, the instructionIncrements r1 by Load register Load and store multiple register instructions Syntax of the LDM instructions is ARM LDM and STM instructionsSyntax WhereUsage LDM and STM addressing modesImplementing stacks with LDM and STM Descending or ascendingStacking registers for nested subroutines Block copy with LDM and STM Example 2-11 Block copyMovs Push and POP Thumb LDM and STM instructionsLDM and STM Thumb-state block copy exampleLSR This macro can be invoked as follows Using macrosTest-and-branch macro example After substitution this becomesAfter the instructions are executed, it holds the remainder Unsigned integer division macro exampleRegister that holds the divisor If only the remainder is requiredRatio DivMod r0,r5,r4,r2 Describing data structures with MAP and Field directives Relative maps Register-based maps Program-relative maps Finding the end of the allocated data Forcing correct alignment EndOfChars Using register-based MAP and Field directives Defining register-based symbolsSetting up a C-type structure Is equivalent to the C codeMaking faster access possible If you want the equivalent of the C code2-27 for an explanation of these This example, the MAP directive is NotField MAP Using two register-based structures Avoiding problems with MAP and Field directives ArrayBase RN r9 Using frame directives Symbols on Expressions, literals, and operators onCommand syntax Specifies that the content of inputfile is read-write Specifies that the content of inputfile is read-onlyPosition-independent. The default is /noropi Position-independent. The default is /norwpiValid options are Assembled for the wrong target FPUSelection of libraries, accordingly Selects no floating-point option. This makes your assembledObject file, for use by the debugger see Keep on Command-line optionsSets the maximum source cache size to n. The default is 8MB Allow unaligned LDRsRegister names First pass and reads them from memory on the second passAs \n and \t Turns off warning messagesAssembler Reference Format of source lines Predeclared program status register names Predefined register and coprocessor namesPredeclared register names Predeclared floating-point register namesBuilt-in variables Lists the built-in variables defined by the ARM assemblerExpressions or conditions, for example Determining the armasm version at assembly time Numeric constants on SymbolsSymbol naming rules Labels onVariables Numeric constantsAssembly time substitution of variables GblsDCQ and Dcqu on DCW and Dcwu on Program-relative labelsDCD and Dcdu on Dcfd and Dcfdu on Dcfs and Dcfsu on Register-relative labelsSyntax of a local label is Syntax of a reference to a local label isAssembler Reference Expressions, literals, and operators This section contains the following subsectionsExample String expressionsString literals String literalsNumeric expressions Numeric literals can take any of the following forms Is a sequence of characters using only the digits 0 to nNumeric literals Numeric code of the characterFloating-point literals Floating-point literals can take any of the following formsLogical literals Register-relative and program-relative expressionsLogical expressions There are only two logical literalsOperator precedence String manipulationOperator precedence in C Precedence Unary operators Operator Usage DescriptionExample of use of SBOFFSET1912 and SBOFFSET11 Binary operators Multiplicative operatorsString manipulation operators Shift operators SHR is a logical shift and does not propagate the sign bitAddition, subtraction, and logical operators Relational operators Boolean operators 10 shows the Boolean operatorsARM DUI 0068B ARM Instruction Reference Add with carry, Add All Logical Branch Move not All ARM condition codes Q flag LDR and STR, halfwords and signed bytes on ARM memory access instructionsLDR and STR, words and unsigned bytes on LDR and STR, doublewords onWhere Is either LDR Load Register or STR Store Register LDR and STR, words and unsigned bytesOtherwise, a 32-bit word is transferred Program-relative Zero offsetPre-indexed offset Post-indexed offsetFlexible offset syntax Address alignment for word transfers Loading to r15Saving from r15 ArchitecturesLDR and STR, halfwords and signed bytes Offset syntax Must be within ±255 bytes of the current instructionIs an offset applied to the value in Rn see Offset syntax Is often a numeric constant see examples belowYou cannot load halfwords or bytes to r15 Offset syntax is the same for LDR and STR, doublewords onAddress alignment for halfword transfers Incorrect exampleMust be an even numbered register, and not r14 LDR and STR, doublewordsIs an optional condition code see Conditional execution on Pre-indexed without writebackNot be the same as Rd or Rd+1 Address alignmentIncorrect examples Increment address after each transfer Is either LDM or STMIs any one of the following Increment address before each transferNon word-aligned addresses Loading or storing the base register, with writeback5 PLD Is the register on which the memory address is basedAlignment Is swapped with the contents of the memory location 6 SWPBoth Rd and Rm ARM general data processing instructions Flexible second operand LSR and LSL Bits of the register are set toCarry flag Instruction substitutionIs the ARM register for the result 2 ADD, SUB, RSB, ADC, SBC, and RSCIs one of ADD, SUB, RSB, ADC, SBC, or RSC Is the ARM register holding the first operandCondition flags Use of r15Multiword arithmetic examples These instructions subtract one 96-bit integer from another 3 AND, ORR, EOR, and BIC Logical AND, OR, Exclusive or and Bit ClearIs one of AND, ORR, EOR, or BIC Orreq MOV and MVN Move and Move NotIs the ARM register for the result Mvnne CMP and CMN Compare and Compare NegativeCMN TST and TEQ Test and Test EquivalenceTEQ Is the ARM register for the result. Rd must not be r15 7 CLZCount Leading Zeroes Is the operand registerARM multiply instructions MUL and MLA onUMULL, UMLAL, Smull and Smlal on MUL and MLA MUL UMULL, UMLAL, Smull and Smlal Is one of UMULL, UMLAL, SMULL, or SmlalUmull Use the top end bits 3116 of Rs SMULxyUse the top end bits 3116 of Rm Are the ARM registers holding the values to be multipliedSmulbt SMLAxy Is the ARM register holding the value to be addedSmlatb SMULWy Use the top end bits 3116 of RsAre the ARM registers holding the operands SMLAWy Are the ARM registers holding the values to be multipliedIs the ARM register holding the value to be added Smlawt SMLALxy Smlaltt Use the top end bits 3116 of Rm 8 MIA, MIAPH, and MIAxyCurrent processors R15 cannot be used for either Rm or RsThese instructions are only available in XScale Is one of QADD, QSUB, QDADD, or Qdsub ARM saturating arithmetic instructionsQADD, QSUB, QDADD, and Qdsub Are the ARM registers holding the operandsQadd ARM branch instructions Branch, and Branch with Link 2 BX 3 BLX Blxmi ARM coprocessor instructions MCR, MCR2, Mcrr on1 CDP, CDP2 Is p n, where n is an integer in the range 2 MCR, MCR2, McrrAre ARM source registers. They must not be r15 3 MRC, MRC2 AffectedMrrc Is an optional suffix specifying a long transfer 5 LDC, STCIs either LDC or STC Is the coprocessor register to load or saveArchitectures 6 LDC2, STC2 Is either LDC2 or STC2Architectures Miscellaneous ARM instructions 1 SWI Software interruptIs the destination register. Rd must not be r15 2 MRSWhere Is either Cpsr or Spsr3 MSR Is either Cpsr or SpsrSee MRS on MSR CPSRf, r5 Bkpt Breakpoint5 MAR, MRA For current processorsAre general-purpose registers Adrl ARM pseudo-instructionon ARM pseudo-instructionsADR ARM pseudo-instructionon LDR ARM pseudo-instruction onIs the register to load ADR ARM pseudo-instructionIs an optional condition code Non word-aligned address within ±255 bytesAdrl ARM pseudo-instruction Non word-aligned address within 64KBWord-aligned address within 256KB R4,start + = ADD R4,pc,#0xe800 LDR ARM pseudo-instruction R3,=0xff0 Loads Into = MOV r3,#0xff0 NOP ARM pseudo-instruction Thumb Instruction Reference Add with carry Rotate right LDR and STR, register offset on Thumb memory access instructionsLDR and STR, immediate offset on LDR and STR, pc or sp relative onLoad register Where Is eitherLDR and STR, immediate offset Store registerAddress alignment for word and halfword transfers LDR and STR, register offset Strsh LDR and STR, pc or sp relative 4 in the range 0 toR2,pc,#1016 POP reglist POP reglist, pc These instructions do not affect the flagsLoad multiple, increment after Ldmia and StmiaLoad and store multiple registers Store multiple, increment afterR3!, r0,r4 ADD, pc or sp relative on Thumb arithmetic instructionsADD and SUB, sp on ADC, SBC, and MUL onADD and SUB, low registers To +7255 to +255 These instructions update the N, Z, C, and V flags Restrictions2 ADD, high or low registers Is a register containing the second operandADD and SUB, sp Range -508 to +508Is either sp or pc 4 ADD, pc or sp relativeIs the destination register. Rd must be in the range r0- r7 RangeWhere Is one of ADC, SBC, or MUL 5 ADC, SBC, and MULMOV, MVN, and NEG on page 5-28 Move, Move NOT, and Negate Thumb general data processing instructionsCMP and CMN on page 5-26 Compare and Compare Negative TST on page 5-30 Test bitsBitwise logical operations Where Is one of AND, ORR, EOR, or BIC1 AND, ORR, EOR, and BIC Range r0- r72 ASR, LSL, LSR, and ROR Register-controlled shift Immediate shiftWhere Is the register containing the first operand Examples Move, Move NOT, and Negate Where Is the destination register4 MOV, MVN, and NEG Is the source registerCondition flags Test bits Where Is the register containing the first operand5 TST Rn and Rm must be in the range r0-r7Thumb branch instructions 3-23 for more information 1 BIs an optional condition code see -2 on Label must be withinCondition codes for Thumb B instruction 2 BL Long branch with Link3 BX Instruction clears the T flag in the CPSR. Code at 4 BLXBranch with Link, and optionally exchange instruction set BLX label always causes a change to ARM stateThumb software interrupt and breakpoint instructions Bkpt onBkpt immed8 Thumb pseudo-instructions ADR Thumb pseudo-instruction 1KB. expr must be defined locally, it cannot be importedLDR Thumb pseudo-instruction If the value of expr is within range of a MOV instruction,Assembler generates the instruction =labelname NOP Thumb pseudo-instruction Syntax for NOP isARM DUI 0068B Vector Floating-point Programming Absolute value Vector All Negate Vector All Vector floating-point coprocessor Reference ManualVFP architectures Floating-point registers Register banksVector stride VectorsVector wrap-around Restriction on vector lengthScalar operations Vector and scalar operationsControl of scalar, vector and mixed operations Vector operationsVFP and condition codes Vector Floating-point Programming VFP system registers FPSCR, the floating-point status and control register0b000 Modifying individual bits of a VFP system register FPEXC, the floating-point exception registerFPSID, the floating-point system ID register See FMRX, FMXR, and Fmstat onFlush-to-zero mode When to use flush-to-zero modeEffects of using flush-to-zero mode Operations not affected by flush-to-zero mode FMRX, FMXR, and Fmstat on VFP instructionsFmrrs and Fmsrr on Ftosi and Ftoui onPage Fabsd d3, d5 Fnegsmi s15, s15 Is the VFP register holding the first operand Fadd and FsubIs the VFP register for the result Is the VFP register holding the second operandWith zero instruction FcmpFloating-point compare Fcmp is always scalar Fcmp instructions can produce Invalid Operation exceptionsFcvtds Is a double-precision VFP register for the resultIs a single-precision VFP register holding the operand Fcvtsd Is a single-precision VFP register for the resultIs a double-precision VFP register holding the operand Fdiv Precision specified in precision FLD and FSTFloating-point load and store Address used for the transferFldsne Fldm and Fstm Unspecified precision Following instructions are equivalentFMAC, FNMAC, FMSC, and Fnmsc Must be one of FMAC, FNMAC, FMSC, or FnmscFnmscsle Are ARM registers. Do not use r15 Fmdrr and FmrrdIs the VFP double-precision register These instructions do not produce any exceptionsFMDHR, FMDLR, FMRDH, and Fmrdl Is the ARM register. Rd must not be r15These instructions are used together as matched pairs Fmrs and Fmsr Is the VFP single-precision registerFmrrs and Fmsrr Are two consecutive VFP single-precision registersAre the ARM registers. Do not use r15 FMRX, FMXR, and Fmstat Is the ARM registerFmul and Fnmul Fsito and Fuito Fsqrt Is the VFP register holding the operandFtosi and Ftoui Is a single-precision VFP register for the integer resultFLD pseudo-instruction VFP pseudo-instructionThere is one VFP pseudo-instruction Can be S for single-precision, or D for double-precisionD1,=3.12E106 Loads 3.12E106 into d1 VFP directives and vector notation Vfpassert Scalar on Vfpassert Vector onVfpassert Scalar VFP directives and vector notation on Vfpassert Vector onWhere Is the vector length Is the vector stride VFP directives and vector notation on Vfpassert Scalar onR10,FPSCR ARM DUI 0068B Assembly control directives on Conditional assembly, looping, inclusions, and macrosAlphabetical list of directives Location of descriptions of directivesGBLA, GBLL, and Gbls on Symbol definition directivesThis section describes the following directives Declare a global arithmetic, logical, or string variableGBLA, GBLL, and Gbls Armasm -pd objectsize Seta 0xFF -o objectfile sourcefile LCLA, LCLL, and Lcls SETA, SETL, and Sets Rlist Names onCoprocessor names on 5 CNCN directive defines a name for a coprocessor register Evaluates to a coprocessor register number from 0 to6 CP Evaluates to a coprocessor number from 0 toDN and SN 8 FN Evaluates to a floating-point register number from 0 toData definition directives DCD and Dcdu onDCQ and Dcqu on Ltorg Set to this address 2 MAPIs a numeric or program-relative expression During the first pass of the assemblerField By the value of exprStorage counter Space Expressions onQuoted string. The characters of the string are loaded into 5 DCBTo 255 see Numeric expressions on Consecutive bytes of storeProgram-relative expression DCD and DcduNumeric expression see Numeric expressions on DCW and Dcwu on DCQ and Dcqu onDcdo Dcfd and Dcfdu Dcfs and Dcfsu 10 DCI Is a numeric expression see Numeric expressions onDCQ and Dcqu DCD and Dcdu on DCW and Dcwu onDCD and Dcdu on DCQ and Dcqu on DCW and DcwuTo 65535 see Numeric expressions on DataMexit on Assembly control directivesMacro and Mend on IF, ELSE, and Endif on While and Wend onMacro and Mend BGE Using a macro to produce assembly-time diagnostics Mexit4 IF, ELSE, and Endif See Relational operators onExample 7-3 Assembly conditional on a variable being defined While and Wend Frame Address on Frame Register on Frame Restore onFrame description directives Frame POP on Frame Push onIs sp unless the function uses a separate frame pointer Can omit itThere are two alternative syntaxes for Frame POP Is the number of bytes that the stack pointer movesFrame Push There are two alternative syntaxes for Frame PushFrame Register Is the register in which the value is preservedFrame Restore Frame Save Frame State Restore on Function or Proc on Frame State RememberFrame State Restore Frame State Remember on Function or Proc onFunction or Proc Endfunc or Endp Reporting directives AssertIs an assertion that can evaluate to either True or False Info Is an expression that evaluates to a stringWhere Is the OPT directive setting. -2 lists valid settings 3 OPTSpecify the -listassembler option to turn on listing OPT TTL and Subt Is the titleIs the subtitle Export or Global on Miscellaneous directivesCODE16 and CODE32 on GET or Include onAlign Cacheable, CODE, ALIGN=3 Area Example,CODE,READONLY An example code section CODE16 and CODE32 4 END Entry Entry directive declares an entry point to a programAddress, or a 32-bit integer constant Is the symbolic name to assign to the value6 EQU Is optional. type can be any oneExport or Global Exportas Extern GET or Include Nesting directives onSee Export or Global on File, or library. The symbol name is case-sensitiveGlobal ImportIncbin IncludeSee GET or Include on Symbols are kept except register-relative symbols KeepRequire Assembly failsNofp Require directive specifies a dependency between sectionsREQUIRE8 and PRESERVE8 19 RN Evaluates to a register number from 0 toRout Thumb state See ARM Developer SuiteAmong other things, computer software PlatformsSee also Saved Processor Status Register Used to find errors in the application program flowDefault thread runs Otherwise statedSee Read Only Position Independent See also RopiSee also Rwpi See Read Write Position IndependentBy ARM to handle semihosting Normally set to zero on resetBlock of software code or data for an Image See Saved Processor Status RegisterIndex Align Gbll Adrl Symbols Index-6