ARM VERSION 1.2 - page 120

ARM Instruction Reference

Address alignment for word transfers

In most circumstances, you must ensure that addresses for 32-bit transfers are 32-bit

word-aligned.

If your system has a system coprocessor (cp15), you can enable alignment checking.

Non word-aligned 32-bit transfers cause an alignment exception if alignment checking

is enabled.

If your system does not have a system coprocessor (cp15), or alignment checking is

disabled:

•For

STR

, the specified address is rounded down to a multiple of four.

•For

LDR

1. The specified address is rounded down to a multiple of four.

2. Four bytes of data are loaded from the resulting address.

3. The loaded data is rotated right by one, two or three bytes according to bits

[1:0] of the address.

For a little-endian memory system, this causes the addressed byte to occupy the

least significant byte of the register.

For a big-endian memory system, it causes the addressed byte to occupy:

—bits[31:24] if bit[0] of the address is 0

—bits[15:8] if bit[0] of the address is 1.

Loading to r15

A load to r15 (the p rogram counter) caus es a branch to the in struction at the addr ess

loaded.

Bits[1:0] of the value loaded:

•are ignored in AR M architecture v 3 and below

•must be zero in ARM architecture v4.

In ARM architecture v5 and above:

•bits[1:0] of a value loaded to r15 must not have the value

0b10

•if bit[0] of a value loaded to r15 is set, the processor changes to Thumb state.

You cannot use the

suffixes when loading to r15.