ARM VERSION 1.2 manual LDR and STR, halfwords and signed bytes

ARM Instruction Reference

4.2.2LDR and STR, halfwords and signed bytes

Load register, signed 8-bit bytes and signed and unsigned 16-bit halfwords.

Store register, 16-bit halfwords.

Signed loads are sign-extended to 32 bits. Unsigned halfword loads are zero-extended to 32 bits.

Syntax

These instructions have four possible forms:

•zero offset

•pre-indexed offset

•program-relative

•post-indexed offset.

The syntax of the four forms, in the same order, are:

op{cond}type Rd, [Rn]

op{cond}type Rd, [Rn, Offset]{!} op{cond}type Rd, label op{cond}type Rd, [Rn], Offset where:

op	is either LDR or STR.
cond	is an optional condition code (see Conditional execution on page 4-4).
type	must be one of:
	SH	for Signed Halfword (LDR only)
	H	for unsigned Halfword
	SB	for Signed Byte (LDR only).
Rd	is the ARM register to load or save.
Rn	is the register on which the memory address is based.
	Rn must not be the same as Rd, if the instruction is either:
	•	pre-indexed with writeback
	•	post-indexed.

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