ARM VERSION 1.2 6.1 The vector floating-point coprocessor

Vector Floating-point Programming

6.1 The vector floating-point coprocessor

The Vector Floating-Point (VFP) coprocessor, together with associated support code,

provides single-precision and double-precision floating-point arithmetic, as defined by

ANSI/IEEE Std. 754-1985 IEEE Standard for Binary Floating-Point Arithmetic. This

document is referred to as the IEEE 754 standard in this chapter. There is a summary of

the standard in the floating-point chapter in ADS Compilers and Libraries Guide.

Short vectors of up to eight single-precision or four double-precision numbers are

handled particularly efficiently. Most arithmetic instructions can be used on these

vectors, allowing single-instruction, multiple-data (SIMD) parallelism. In addition, the

floating-point load and store instructions have multiple register forms, allowing vectors

to be transferred to and from memory efficiently.

For further details of the vector floating-point coprocessor, see ARM Architecture

Reference Manual.

6.1.1 VFP architectures

There are two versions of the VFP architecture. VFPv 2 has all the instructions tha t

VFPv1 has, and four additional instructions.

The additional instructions allow you to transfer two 32-bit words between ARM

registers and VFP registers with one instruction.