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Vector Floating-point Programming

6.9.2VFPASSERT VECTOR

The VFPASSERT VECTOR directive informs the assembler that following VFP instructions are in vector mode. It can also specify the length and stride of the vectors.

Syntax

VFPASSERT VECTOR[<[n[:s]]>]

where:

nis the vector length, 1-8.

sis the vector stride, 1-2.

Usage

Use the VFPASSERT VECTOR directive to mark the start of a block of instructions where the VFP mode is VECTOR, and to mark changes in the length or stride of vectors.

Place the VFPASSERT VECTOR directive immediately after the instruction where the change occurs. This is usually an FMXR instruction, but might be a BL instruction.

If a function expects the VFP to be in vector mode on entry, place a VFPASSERT VECTOR directive immediately before the first instruction. Such a function would not be ATPCS conformant. See the Using the Procedure Call Standard chapter in ADS Developer Guide for further information.

See:

•VFP directives and vector notation on page 6-40

•VFPASSERT SCALAR on page 6-41.

Note

This directive does not generate any code. It is only an assertion by the programmer. The assembler produces error messages if any such assertions are inconsistent with each other, or with any vector notation in VFP data processing instructions.

6-42

Copyright © 2000, 2001 ARM Limited. All rights reserved.

ARM DUI 0068B

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ARM VERSION 1.2 Where Is the vector length Is the vector stride, VFP directives and vector notation on Vfpassert Scalar on

Contents

ARM Developer Suite Assembler Guide ARM Developer SuiteCopyright 2000, 2001 ARM Limited. All rights reserved ARM Developer Suite Assembler Guide Glossary About this book on Feedback onUsing this book About this bookIntended audience This book is organized into the following chaptersTypographical conventions ItalicFurther reading ARM publicationsARM Reference Peripheral Specification ARM DDI Other publicationsFeedback on the ARM Developer Suite FeedbackFeedback on this book ARM DUI 0068B Introduction About the ARM Developer Suite assemblers onAbout the ARM Developer Suite assemblers ARM Developer Suite ADS hasWriting ARM and Thumb Assembly Language Code examples IntroductionOr run the module in AXD with interleaving on See Overview of the ARM architecture Architecture versionsARM and Thumb state ARM processors always start executing code in ARM stateRegisters Processor modeGeneral-purpose, 32-bit registers Program counter pc Branch instructions ARM instruction set overviewData processing instructions Status register access instructions Single register load and store instructionsMultiple register load and store instructions Semaphore instructionsRegister access Access to the inline barrel shifterARM instruction capabilities Following general points apply to ARM instructionsThumb instruction capabilities Thumb instruction set overviewFollowing general points apply to Thumb instructions Access to the barrel shifter Differences between Thumb and ARM instruction setsSingle register load and store instructions Structure of assembly language modules Layout of assembly language source filesGeneral form of source lines in assembly language is Case rulesLocal labels LabelsComments Constants Is a base between 2 Xxx is a number in that baseAn example ARM assembly language module ELF sections and the Area directiveEntry directive Application executionApplication termination END directiveCalling subroutines CODE32 and CODE16 directives An example Thumb assembly language moduleBX instruction Using the C preprocessor Example 2-4 Preprocessing an assembly language source fileConditional execution ALU status flagsExecution conditions ExamplesUsing conditional execution in ARM state Example of the use of conditional executionConditional branches only Converting to Thumb Branch prediction and cachesLoading constants into registers Direct loading with MOV and MVN Right, 2 bitsDirect loading with MOV in Thumb state Loading with LDR Rd, =constPlacing literal pools Loading floating-point constants Loading addresses into registers Direct loading with ADR and AdrlADR Implementing a jump table with ADR Example 2-7 ARM code jump table Example 2-8 Thumb code jump table Loading addresses with LDR Rd, = label R1, =Darea + = LDR R1,PC, #offset into Literal Pool Address registers. For example, the instruction An LDR Rd, =label example string copyingIncrements r1 by Load register Load and store multiple register instructions ARM LDM and STM instructions SyntaxSyntax of the LDM instructions is WhereUsage LDM and STM addressing modesImplementing stacks with LDM and STM Descending or ascendingStacking registers for nested subroutines Block copy with LDM and STM Example 2-11 Block copyMovs Thumb LDM and STM instructions LDM and STMPush and POP Thumb-state block copy exampleLSR Using macros Test-and-branch macro exampleThis macro can be invoked as follows After substitution this becomesUnsigned integer division macro example Register that holds the divisorAfter the instructions are executed, it holds the remainder If only the remainder is requiredRatio DivMod r0,r5,r4,r2 Describing data structures with MAP and Field directives Relative maps Register-based maps Program-relative maps Finding the end of the allocated data Forcing correct alignment EndOfChars Using register-based MAP and Field directives Defining register-based symbolsSetting up a C-type structure Is equivalent to the C codeIf you want the equivalent of the C code Making faster access possible2-27 for an explanation of these This example, the MAP directive is NotField MAP Using two register-based structures Avoiding problems with MAP and Field directives ArrayBase RN r9 Using frame directives Symbols on Expressions, literals, and operators onCommand syntax Specifies that the content of inputfile is read-only Position-independent. The default is /noropiSpecifies that the content of inputfile is read-write Position-independent. The default is /norwpiAssembled for the wrong target FPU Selection of libraries, accordinglyValid options are Selects no floating-point option. This makes your assembledCommand-line options Sets the maximum source cache size to n. The default is 8MBObject file, for use by the debugger see Keep on Allow unaligned LDRsFirst pass and reads them from memory on the second pass As \n and \tRegister names Turns off warning messagesAssembler Reference Format of source lines Predefined register and coprocessor names Predeclared register namesPredeclared program status register names Predeclared floating-point register namesLists the built-in variables defined by the ARM assembler Built-in variablesExpressions or conditions, for example Determining the armasm version at assembly time Symbols Symbol naming rulesNumeric constants on Labels onVariables Numeric constantsAssembly time substitution of variables GblsProgram-relative labels DCD and Dcdu on Dcfd and Dcfdu on Dcfs and Dcfsu onDCQ and Dcqu on DCW and Dcwu on Register-relative labelsSyntax of a local label is Syntax of a reference to a local label isAssembler Reference Expressions, literals, and operators This section contains the following subsectionsString expressions String literalsExample String literalsNumeric expressions Is a sequence of characters using only the digits 0 to n Numeric literalsNumeric literals can take any of the following forms Numeric code of the characterFloating-point literals Floating-point literals can take any of the following formsRegister-relative and program-relative expressions Logical expressionsLogical literals There are only two logical literalsOperator precedence String manipulationOperator precedence in C Precedence Unary operators Operator Usage DescriptionExample of use of SBOFFSET1912 and SBOFFSET11 Multiplicative operators Binary operatorsString manipulation operators SHR is a logical shift and does not propagate the sign bit Shift operatorsAddition, subtraction, and logical operators Relational operators Boolean operators 10 shows the Boolean operatorsARM DUI 0068B ARM Instruction Reference Add with carry, Add All Logical Branch Move not All ARM condition codes Q flag ARM memory access instructions LDR and STR, words and unsigned bytes onLDR and STR, halfwords and signed bytes on LDR and STR, doublewords onLDR and STR, words and unsigned bytes Where Is either LDR Load Register or STR Store RegisterOtherwise, a 32-bit word is transferred Zero offset Pre-indexed offsetProgram-relative Post-indexed offsetFlexible offset syntax Address alignment for word transfers Loading to r15Saving from r15 ArchitecturesLDR and STR, halfwords and signed bytes Must be within ±255 bytes of the current instruction Is an offset applied to the value in Rn see Offset syntaxOffset syntax Is often a numeric constant see examples belowOffset syntax is the same for LDR and STR, doublewords on Address alignment for halfword transfersYou cannot load halfwords or bytes to r15 Incorrect exampleLDR and STR, doublewords Is an optional condition code see Conditional execution onMust be an even numbered register, and not r14 Pre-indexed without writebackNot be the same as Rd or Rd+1 Address alignmentIncorrect examples Is either LDM or STM Is any one of the followingIncrement address after each transfer Increment address before each transferNon word-aligned addresses Loading or storing the base register, with writeback5 PLD Is the register on which the memory address is basedAlignment 6 SWP Is swapped with the contents of the memory locationBoth Rd and Rm ARM general data processing instructions Flexible second operand LSR and LSL Bits of the register are set toCarry flag Instruction substitution2 ADD, SUB, RSB, ADC, SBC, and RSC Is one of ADD, SUB, RSB, ADC, SBC, or RSCIs the ARM register for the result Is the ARM register holding the first operandUse of r15 Condition flagsMultiword arithmetic examples These instructions subtract one 96-bit integer from another Logical AND, OR, Exclusive or and Bit Clear 3 AND, ORR, EOR, and BICIs one of AND, ORR, EOR, or BIC Orreq Move and Move Not MOV and MVNIs the ARM register for the result Mvnne CMP and CMN Compare and Compare NegativeCMN TST and TEQ Test and Test EquivalenceTEQ 7 CLZ Count Leading ZeroesIs the ARM register for the result. Rd must not be r15 Is the operand registerMUL and MLA on ARM multiply instructionsUMULL, UMLAL, Smull and Smlal on MUL and MLA MUL UMULL, UMLAL, Smull and Smlal Is one of UMULL, UMLAL, SMULL, or SmlalUmull SMULxy Use the top end bits 3116 of RmUse the top end bits 3116 of Rs Are the ARM registers holding the values to be multipliedSmulbt SMLAxy Is the ARM register holding the value to be addedSmlatb Use the top end bits 3116 of Rs SMULWyAre the ARM registers holding the operands Are the ARM registers holding the values to be multiplied SMLAWyIs the ARM register holding the value to be added Smlawt SMLALxy Smlaltt 8 MIA, MIAPH, and MIAxy Current processorsUse the top end bits 3116 of Rm R15 cannot be used for either Rm or RsThese instructions are only available in XScale ARM saturating arithmetic instructions QADD, QSUB, QDADD, and QdsubIs one of QADD, QSUB, QDADD, or Qdsub Are the ARM registers holding the operandsQadd ARM branch instructions Branch, and Branch with Link 2 BX 3 BLX Blxmi ARM coprocessor instructions MCR, MCR2, Mcrr on1 CDP, CDP2 2 MCR, MCR2, Mcrr Is p n, where n is an integer in the rangeAre ARM source registers. They must not be r15 3 MRC, MRC2 AffectedMrrc 5 LDC, STC Is either LDC or STCIs an optional suffix specifying a long transfer Is the coprocessor register to load or saveArchitectures 6 LDC2, STC2 Is either LDC2 or STC2Architectures Miscellaneous ARM instructions 1 SWI Software interrupt2 MRS WhereIs the destination register. Rd must not be r15 Is either Cpsr or SpsrIs either Cpsr or Spsr 3 MSRSee MRS on MSR CPSRf, r5 Bkpt BreakpointFor current processors 5 MAR, MRAAre general-purpose registers ARM pseudo-instructions ADR ARM pseudo-instructiononAdrl ARM pseudo-instructionon LDR ARM pseudo-instruction onADR ARM pseudo-instruction Is an optional condition codeIs the register to load Non word-aligned address within ±255 bytesNon word-aligned address within 64KB Adrl ARM pseudo-instructionWord-aligned address within 256KB R4,start + = ADD R4,pc,#0xe800 LDR ARM pseudo-instruction R3,=0xff0 Loads Into = MOV r3,#0xff0 NOP ARM pseudo-instruction Thumb Instruction Reference Add with carry Rotate right Thumb memory access instructions LDR and STR, immediate offset onLDR and STR, register offset on LDR and STR, pc or sp relative onWhere Is either LDR and STR, immediate offsetLoad register Store registerAddress alignment for word and halfword transfers LDR and STR, register offset Strsh LDR and STR, pc or sp relative 4 in the range 0 toR2,pc,#1016 POP reglist POP reglist, pc These instructions do not affect the flagsLdmia and Stmia Load and store multiple registersLoad multiple, increment after Store multiple, increment afterR3!, r0,r4 Thumb arithmetic instructions ADD and SUB, sp onADD, pc or sp relative on ADC, SBC, and MUL onTo +7 ADD and SUB, low registers255 to +255 These instructions update the N, Z, C, and V flags Restrictions2 ADD, high or low registers Is a register containing the second operandADD and SUB, sp Range -508 to +5084 ADD, pc or sp relative Is the destination register. Rd must be in the range r0- r7Is either sp or pc RangeWhere Is one of ADC, SBC, or MUL 5 ADC, SBC, and MULThumb general data processing instructions CMP and CMN on page 5-26 Compare and Compare NegativeMOV, MVN, and NEG on page 5-28 Move, Move NOT, and Negate TST on page 5-30 Test bitsWhere Is one of AND, ORR, EOR, or BIC 1 AND, ORR, EOR, and BICBitwise logical operations Range r0- r72 ASR, LSL, LSR, and ROR Register-controlled shift Immediate shiftWhere Is the register containing the first operand Examples Where Is the destination register 4 MOV, MVN, and NEGMove, Move NOT, and Negate Is the source registerCondition flags Where Is the register containing the first operand 5 TSTTest bits Rn and Rm must be in the range r0-r7Thumb branch instructions 1 B Is an optional condition code see -2 on3-23 for more information Label must be withinCondition codes for Thumb B instruction 2 BL Long branch with Link3 BX 4 BLX Branch with Link, and optionally exchange instruction setInstruction clears the T flag in the CPSR. Code at BLX label always causes a change to ARM stateThumb software interrupt and breakpoint instructions Bkpt onBkpt immed8 Thumb pseudo-instructions ADR Thumb pseudo-instruction 1KB. expr must be defined locally, it cannot be importedIf the value of expr is within range of a MOV instruction, LDR Thumb pseudo-instructionAssembler generates the instruction =labelname NOP Thumb pseudo-instruction Syntax for NOP isARM DUI 0068B Vector Floating-point Programming Absolute value Vector All Negate Vector All Reference Manual Vector floating-point coprocessorVFP architectures Floating-point registers Register banksVectors Vector wrap-aroundVector stride Restriction on vector lengthVector and scalar operations Control of scalar, vector and mixed operationsScalar operations Vector operationsVFP and condition codes Vector Floating-point Programming VFP system registers FPSCR, the floating-point status and control register0b000 FPEXC, the floating-point exception register FPSID, the floating-point system ID registerModifying individual bits of a VFP system register See FMRX, FMXR, and Fmstat onWhen to use flush-to-zero mode Flush-to-zero modeEffects of using flush-to-zero mode Operations not affected by flush-to-zero mode VFP instructions Fmrrs and Fmsrr onFMRX, FMXR, and Fmstat on Ftosi and Ftoui onPage Fabsd d3, d5 Fnegsmi s15, s15 Fadd and Fsub Is the VFP register for the resultIs the VFP register holding the first operand Is the VFP register holding the second operandFcmp Floating-point compare Fcmp is always scalarWith zero instruction Fcmp instructions can produce Invalid Operation exceptionsIs a double-precision VFP register for the result FcvtdsIs a single-precision VFP register holding the operand Is a single-precision VFP register for the result FcvtsdIs a double-precision VFP register holding the operand Fdiv FLD and FST Floating-point load and storePrecision specified in precision Address used for the transferFldsne Fldm and Fstm Unspecified precision Following instructions are equivalentFMAC, FNMAC, FMSC, and Fnmsc Must be one of FMAC, FNMAC, FMSC, or FnmscFnmscsle Fmdrr and Fmrrd Is the VFP double-precision registerAre ARM registers. Do not use r15 These instructions do not produce any exceptionsIs the ARM register. Rd must not be r15 FMDHR, FMDLR, FMRDH, and FmrdlThese instructions are used together as matched pairs Fmrs and Fmsr Is the VFP single-precision registerAre two consecutive VFP single-precision registers Fmrrs and FmsrrAre the ARM registers. Do not use r15 FMRX, FMXR, and Fmstat Is the ARM registerFmul and Fnmul Fsito and Fuito Fsqrt Is the VFP register holding the operandFtosi and Ftoui Is a single-precision VFP register for the integer resultVFP pseudo-instruction There is one VFP pseudo-instructionFLD pseudo-instruction Can be S for single-precision, or D for double-precisionD1,=3.12E106 Loads 3.12E106 into d1 VFP directives and vector notation Vfpassert Scalar on Vfpassert Vector onVfpassert Scalar VFP directives and vector notation on Vfpassert Vector onWhere Is the vector length Is the vector stride VFP directives and vector notation on Vfpassert Scalar onR10,FPSCR ARM DUI 0068B Assembly control directives on Conditional assembly, looping, inclusions, and macrosAlphabetical list of directives Location of descriptions of directivesSymbol definition directives This section describes the following directivesGBLA, GBLL, and Gbls on Declare a global arithmetic, logical, or string variableGBLA, GBLL, and Gbls Armasm -pd objectsize Seta 0xFF -o objectfile sourcefile LCLA, LCLL, and Lcls SETA, SETL, and Sets Rlist Names on5 CN CN directive defines a name for a coprocessor registerCoprocessor names on Evaluates to a coprocessor register number from 0 to6 CP Evaluates to a coprocessor number from 0 toDN and SN 8 FN Evaluates to a floating-point register number from 0 toDCD and Dcdu on Data definition directivesDCQ and Dcqu on Ltorg 2 MAP Is a numeric or program-relative expressionSet to this address During the first pass of the assemblerBy the value of expr FieldStorage counter Space Expressions on5 DCB To 255 see Numeric expressions onQuoted string. The characters of the string are loaded into Consecutive bytes of storeDCD and Dcdu Numeric expression see Numeric expressions onProgram-relative expression DCW and Dcwu on DCQ and Dcqu onDcdo Dcfd and Dcfdu Dcfs and Dcfsu 10 DCI Is a numeric expression see Numeric expressions onDCQ and Dcqu DCD and Dcdu on DCW and Dcwu onDCW and Dcwu To 65535 see Numeric expressions onDCD and Dcdu on DCQ and Dcqu on DataAssembly control directives Macro and Mend onMexit on IF, ELSE, and Endif on While and Wend onMacro and Mend BGE Using a macro to produce assembly-time diagnostics Mexit4 IF, ELSE, and Endif See Relational operators onExample 7-3 Assembly conditional on a variable being defined While and Wend Frame Register on Frame Restore on Frame description directivesFrame Address on Frame POP on Frame Push onIs sp unless the function uses a separate frame pointer Can omit itThere are two alternative syntaxes for Frame POP Is the number of bytes that the stack pointer movesFrame Push There are two alternative syntaxes for Frame PushFrame Register Is the register in which the value is preservedFrame Restore Frame Save Frame State Restore on Function or Proc on Frame State RememberFrame State Restore Frame State Remember on Function or Proc onFunction or Proc Endfunc or Endp Assert Reporting directivesIs an assertion that can evaluate to either True or False Info Is an expression that evaluates to a string3 OPT Where Is the OPT directive setting. -2 lists valid settingsSpecify the -listassembler option to turn on listing OPT Is the title TTL and SubtIs the subtitle Miscellaneous directives CODE16 and CODE32 onExport or Global on GET or Include onAlign Cacheable, CODE, ALIGN=3 Area Example,CODE,READONLY An example code section CODE16 and CODE32 4 END Entry Entry directive declares an entry point to a programIs the symbolic name to assign to the value 6 EQUAddress, or a 32-bit integer constant Is optional. type can be any oneExport or Global Exportas Extern GET or Include Nesting directives onFile, or library. The symbol name is case-sensitive GlobalSee Export or Global on ImportInclude IncbinSee GET or Include on Symbols are kept except register-relative symbols KeepAssembly fails NofpRequire Require directive specifies a dependency between sectionsREQUIRE8 and PRESERVE8 19 RN Evaluates to a register number from 0 toRout See ARM Developer Suite Among other things, computer softwareThumb state PlatformsUsed to find errors in the application program flow Default thread runsSee also Saved Processor Status Register Otherwise statedSee also Ropi See also RwpiSee Read Only Position Independent See Read Write Position IndependentNormally set to zero on reset Block of software code or data for an ImageBy ARM to handle semihosting See Saved Processor Status RegisterIndex Align Gbll Adrl Symbols Index-6