Vector Floating-point Programming
6-30 Copyright © 2000, 2001 ARM Limited. A ll rights reserved. ARM DUI 0068B
6.7.11 FMDHR, FMDLR, FMRDH, and FMRDL
Transfer contents between an ARM register and a half of a double-precision
floating-point register.
Syntax
FMDHR{cond} Dn, Rd
FMDLR{cond} Dn, Rd
FMRDH{cond} Rd, Dn
FMRDL{cond} Rd, Dn
where:
cond
is an optional condition code (see VFP and condition codes on page6-8).
Dn
is the VFP double-precision register.
Rd
is the ARM register.
Rd
must not be r1 5.
Usage
These instructions are used to gether as matched pairs:
•Use
FMDHR
with
FMDLR
FMDHR
copy the contents of
Rd
into the high half of
Dn
FMDLR
copy the contents of
Rd
into the low half of
Dn
•Use
FMRDH
with
FMRDL
FMRDH
copy the contents of the high half of
Dn
into
Rd
FMRDL
copy the contents of the low half of
Dn
into
Rd
.
Exceptions
These instructions do not produce any exceptions.
Examples
FMDHR d5, r3
FMDLR d5, r12
FMRDH r5, d3
FMRDL r9, d3
FMDLRPL d2, r1