ARM VERSION 1.2 manual VFP system registers, FPSCR, the floating-point status and control register

Vector Floating-point Programming

6.5VFP system registers

Three VFP system registers are accessible to you in all implementations of VFP:

•FPSCR, the floating-point status and control register

•FPEXC, the floating-point exception register on page 6-12

•FPSID, the floating-point system ID register on page 6-12.

A particular implementation of VFP can have additional registers (see the technical reference manual for the VFP coprocessor you are using).

6.5.1FPSCR, the floating-point status and control register

The FPSCR contains all the user-level VFP status and control bits:

bits[31:28] are the N, Z, C, and V flags. These are the VFP status flags. They cannot be used to control conditional execution until they have been copied into the status flags in the CPSR (see VFP and condition codes on page 6-8).

bit[24] is the flush-to-zero mode control bit:

0flush-to-zero mode is disabled.

1flush-to-zero mode is enabled.

Flush-to-zero mode can allow greater performance, depending on your hardware and software, at the expense of loss of range (see Flush-to-zero mode on page 6-13).

Note

Flush-to-zero mode must not be used when IEEE 754 compatibility is a requirement.

bits[23:22] control rounding mode as follows:

0b00 Round to Nearest (RN) mode

0b01 Round towards Plus infinity (RP) mode

0b10 Round towards Minus infinity (RM) mode

0b11 Round towards Zero (RZ) mode.

bits[21:20] STRIDE is the distance between successive values in a vector (see Vectors on page 6-6). Stride is controlled as follows:

0b00	stride = 1
0b11	stride = 2.

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